All Courses
All Courses Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
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Computational Fluid Dynamics
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Custom IC / Analog / Microwave & RF Design
Circuit Design and Simulation- Analog Circuit Design and Simulation Onboarding
- Analog Modeling and Simulation with SPICE
- Design Checks and Asserts
- High-Performance Spectre Simulation
- Spectre FMC in Virtuoso ADE
- Spectre FX Simulator
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso Schematic Editor
- Virtuoso Spectre Pro S1: DC Algorithm
- Virtuoso Spectre Pro S2: Transient Algorithm
- Virtuoso Spectre Transient Noise
- Virtuoso System Design Platform
- Virtuoso Visualization and Analysis
Mixed-Signal Modeling and Simulation- Analog Modeling with Verilog-A
- Behavioral Modeling with Verilog-AMS
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Mixed Signal Simulations Using Spectre AMS Designer
- Mixed Signal Verification with UVM
- Real Modeling with SystemVerilog
- Real Modeling with Verilog-AMS
- SimVision for Debugging Mixed-Signal Simulations
- SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
Physical Design- Dependable Connectivity-Driven Layout with Virtuoso Studio
- Virtuoso Abstract Generator
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Design Basics
- Virtuoso Layout Onboarding
- Virtuoso Layout Pro: T1 Environment and Basic Commands
- Virtuoso Layout Pro: T2 Create and Edit Commands
- Virtuoso Layout Pro: T3 Basic Commands
- Virtuoso Layout Pro: T4 Advanced Commands
- Virtuoso Layout Pro: T5 Interactive Routing
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner
- Virtuoso Layout Pro: T8 Virtuoso Concurrent Layout Editing
- Virtuoso Layout Pro: T9 Virtuoso Design Planner
- Virtuoso Layout for Advanced Nodes and Methodology Platform
- Virtuoso Simulation Driven Routing (SDR)
Physical Verification- Pegasus Verification System
- Physical Verification Language Rules Writer
- Physical Verification System
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- Virtuoso Layout Pro: T4 Advanced Commands
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Custom IC / Analog / RF Design
Circuit Design and Simulation- Analog Modeling and Simulation with SPICE
- Design Checks and Asserts
- High-Performance Spectre Simulation
- Mixed Signal Simulations Using Spectre AMS Designer
- Simulation and Analysis Using OCEAN
- Spectre Accelerated Parallel Simulator
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
- Variation Analysis Using the Virtuoso Variation Option
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso Analog Design Environment
- Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
- Virtuoso Schematic Editor
- Virtuoso Spectre Pro S1: DC Algorithm
- Virtuoso System Design Platform
- Virtuoso Visualization and Analysis
Circuit Simulation- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Mixed Signal Simulations Using Spectre AMS Designer
- Real Modeling with SystemVerilog
- Simulation and Analysis Using OCEAN
- Spectre Accelerated Parallel Simulator
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Virtuoso Spectre Pro S2: AC, XF, STB, and Noise Analyses
- Virtuoso Spectre Pro S3: Transient Algorithm
- Virtuoso Spectre Pro S4: Measuring Accurate Fourier Transforms
- Virtuoso Spectre Pro S5: Transient Noise
- Virtuoso UltraSim Full-chip Simulator
Physical Design- Enhancing Layout Productivity with Virtuoso Layout Pro Training Webinar
- Pegasus Verification System
- Physical Verification System
- Quantus Transistor-Level T2: Parasitic Extraction
- SKILL Language Programming Introduction
- Virtuoso Abstract Generator
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
- Virtuoso Layout Pro: T2 Create and Edit Commands (L)
- Virtuoso Layout Pro: T3 Basic Commands (XL)
- Virtuoso Layout Pro: T4 Advanced Commands (XL)
- Virtuoso Layout Pro: T5 Interactive Routing (XL)
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
- Virtuoso Layout Pro: T8 Debugging Layout Issues
- Virtuoso Layout Pro: T9 Virtuoso Design Planner
- Virtuoso Layout for Advanced Nodes and Methodology Platform
- Virtuoso Simulation Driven Routing (SDR)
- Virtuoso Space-Based Router
- Virtuoso Space-Based Router Express
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Digital Design and Signoff
Implementation- Artificial Intelligence and Machine Learning Fundamentals
- Cadence Cerebrus Intelligent Chip Explorer
- Innovus Block Implementation with Stylus Common UI
- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Clock Concurrent Optimization Technology with Stylus Common UI
- Innovus Hierarchical Implementation with Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Innovus Low-Power Flow with Stylus Common UI
- Low-Power Flow with Innovus Implementation System
- Virtuoso Digital Implementation
Synthesis and Test- ATPG Flow with Modus DFT Software Solution
- Advanced Synthesis with Genus Stylus Common UI
- Design for Test Fundamentals
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Low-Power Synthesis Flow with IEEE 1801
- Genus Synthesis Solution with Stylus Common UI
- Joules Power Calculator
- Low-Power Synthesis Flow with Genus Stylus Common UI
- Test Synthesis with Genus Stylus Common UI
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IC Package
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Languages and Methodologies
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Mixed-Signal Design Modeling, Simulation and Verification
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Onboarding Curricula
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PCB Design
Design Authoring- Allegro Design Entry HDL SKILL Programming Language
- Allegro Design Reuse
- Allegro EDM Design Entry HDL Front-to-Back Flow
- Allegro FPGA System Planner
- Allegro System Architect
- Allegro System Capture
- Allegro Team Design Authoring
- Allegro X Design Entry HDL Basics
- Allegro X Design Entry HDL Front-to-Back Flow
- Allegro X System Capture Basics
- OrCAD CIS
- OrCAD Capture Constraint Manager PCB Flow
- OrCAD X Capture
PCB Layout- Advanced Design Verification with the RAVEL Programming Language
- Allegro DesignTrue DFM
- Allegro High-Speed Constraint Management
- Allegro PCB Editor Advanced Methodologies
- Allegro PCB Editor Intermediate Techniques
- Allegro PCB Editor SKILL Programming Language
- Allegro PCB Router Basics
- Allegro RF PCB
- Allegro X PCB Editor Basic Techniques
- Allegro X Update Training
- DFM-Aware PCB Design Using Allegro DesignTrue Technology (Webinar)
- OrCAD X Presto Basic Techniques
- PCB Layout Designer Onboarding
SI/PI Analysis Point Tools- Celsius Thermal Solver
- Clarity 3D Solver
- Essential High-Speed PCB Design for Signal Integrity
- Model Generation and Analysis using PowerSI and Broadband SPICE
- Sigrity Aurora
- Sigrity PowerDC and OptimizePI
- Sigrity PowerDC and OptimizePI (Français)
- Sigrity SystemSI for Parallel Bus and Serial Link Analysis
- SystemSI for Parallel Bus and Serial Link Analysis
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System Design and Verification
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Tech Domain Certification Programs
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Tensilica Processor IP
Tensilica Processors- Tensilica Instruction Extension Language and Design
- Tensilica System Modeling using XTSC
- Tensilica Xtensa LX Hardware Verification and EDA
- Tensilica Xtensa LX Processor Fundamentals
- Tensilica Xtensa LX Processor Interfaces
- Tensilica Xtensa NX Hardware Verification and EDA
- Tensilica Xtensa NX Processor Fundamentals
- Tensilica Xtensa NX Processor Interfaces