Specman Fundamentals for Block-Level Environment Developers Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
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13.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 5 days
Course Description
In this course, you learn how to create a reusable block-level verification environment with the e language for the Xcelium™ simulator.
The course provides an introduction to the e language and the Coverage-Driven Verification (CDV) methodology. The reusable verification environment is built using the industry-standard Universal Verification Methodology (UVM-e).
Learning Objectives
After completing this course, you will be able to:
- Describe the differences between Coverage-Driven Verification (CDV) and directed tests
- Create reusable verification components (UVCs) that comply with the UVM methodology
- Control stimulus generation using sequences, virtual sequences, and the built-in sequence API
- Write and debug regular methods and time consuming methods (TCMs)
- Use Specman® and SimVision™ debugging features
- Define, collect, and analyze functional coverage information
- Use scoreboarding and assertions to perform data and timing checks
- Implement the end of test and reset methodologies
Software Used in This Course
- Xcelium Single-Core
Software Release(s)
XCELIUM1710
Modules in this Course
- Introduction to Coverage-Driven Verification (CDV)
- e Language Basics
- Generation
- When Inheritance (AOP Inheritance)
- Connecting and Interacting with the DUT
- Checking DUT Behavior
- Developing Coverage
- Development of an Interface UVM Verification Component
- Developing Sequences
- Development of Module/Sub-System UVM Verification Components
- Handling Reset and End-Of-Test
Audience
- Design and Verification Engineers
Prerequisites
You must have experience with or knowledge of the following:
- Any Object-Oriented Language, such as C++, C#, SystemVerilog for Testbenches, Java or Python
Related Courses
“The training has helped me to get a better understanding on how to make the verification environment more structured. The pace was good. All the labs were effective.”
Sindhu Joseph, Intel
“The course was very good! Awesome instructor. He is very friendly and competent in this topic.”
Rafet Ogul Tuerkel, Robert Bosch
“I am completely satisfied with the training. I learned a lot. I can feel an instant improvement. The training material was well organized and topics presented are of great usage.(...) I feel I enormously improved my knowledge. Thank you for this nice training!”
Marko Ilic, Infineon Technologies
“The Cadence Specman training is a great way of learning the e language, the Specman tool, and the Universal Verification Methodology (UVM).(...) I highly recommend this Cadence training.”
Raimund Soenning, Fujitsu
“This is the best online course I have attended so far.”
Robert Szczygiel, AGH University of Science and Technology
“I liked the in-depth knowledge of the instructor on specman/e and his passion/motivation on sharing this knowledge.”
Artemios Diakogiannis, Bosch Sensortec
"I really enjoyed the course and learned a lot. I especially liked the labs. With the labs it is much easier to understand everything that was covered in the lectures."
Francisco Torres, Broadcom
"My impression of the Specman training(...)is that it was extremely well done and it should help me in developing some reasonable knowledge of that language. It has also been very useful to follow the online training before the training in the class."
Dario Cardini, Robert Bosch