Tensilica Instruction Extension Language and Design Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
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6.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 1 day
Course Description
This one-day training class introduces Tensilica® Instruction Extensions (TIE) and teaches the basics of writing TIE. You will be introduced to some of the most useful TIE constructs, their syntax, and examples of how to use them. You will learn how to create processor extensions that improve the processing performance as well as data bandwidth for your application code. Four labs covering different topics will provide hands-on experience in writing TIE code. This class is highly recommended for designers writing TIE or for those interested in learning about the TIE processor extension methodology.
Learning Objectives
After completing this course, you will be able to:
- Create TIE instruction extensions for an Xtensa® processor core
- Use TIE instructions in your application software to improve performance
- Ensure efficient hardware implementation of your TIE instructions
Software Used in This Course
- Xtensa Software Tools Release RF-2014.2
Software Release(s)
- RF-2014.2
Modules in this Course
TIE Introduction
- Overview of TIE
- Design Flow
- Typical Instruction Extensions
Creating and Using Instruction Extensions
- TIE Operation: Creating a New Instruction
- TIE Intrinsic: Using Instruction in C/C++ Code
- Lab: Endian Conversion
- TIE Verification
Scheduling TIE Operations
- TIE Schedule: Creating Multi-Cycle Operations
- TIE Wire: Creating Complex Expressions
Improving Performance via Instruction-Level Parallelism
- Defining and Using FLIX Instructions
- Lab: FLIX
Adding Architectural Storage to Cores
- TIE State: Adding Single Registers
- TIE Regfile: Adding Register Files
- TIE CType: Custom C/C++ Data Types
- Lab: Creating and Using Register Files
Maximizing Re-use
- Reusing Register Files
- Reusing TIE operations
- Operator Overloading
- Creating Single Data Path for Multiple TIE Operations
- Lab: Using TIE Semantics
Designing Custom Load/Store Operations
- Custom Load/Store Instructions
- Compiler-Inferred Loads/Stores
Interfacing with SOC
- TIE Ports for Generalized I/O
- TIE Queue Interfaces for Self-Synchronizing High-Throughput Data Flow
- TIE Lookup Interfaces for Generalized Memory Storage
Audience
- Architects/Designers creating TIE extensions to an Xtensa processor for a specific application
- Other software/hardware engineers working extensively with Xtensa processors
Prerequisites
You must have experience with or knowledge of the following:
- Basic microprocessor architecture
- Programming in C/C++ for software engineers
- RTL design for hardware engineers