Innovus Implementation System (Block) Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
17.1 | Online | ENROLL |
16.2 | Online | ENROLL |
16.1 | Online | ENROLL |
15.2 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 3 days
Course Description
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In this course, you learn how to use the Innovus™ Implementation System software to achieve the best power, performance and area (PPA) for your design. You learn several techniques for floorplanning, and placement using the GigaPlace™ solver-based placement while implementing timing closure strategies with a multi-threaded, layer-aware timing and power-driven optimization engine to reduce dynamic and leakage power. You will learn how to set up and run the concurrent clock and datapath optimization engine to enhance cross-corner variability and boost performance with reduced power.
You run the slack-driven router with track-aware timing optimization which enables you to achieve the multiple objectives that are a part of today's design requirements. You will learn how to diagnose and fix routing violations as well as explore challenges and solutions for design implementation in nodes that are 20nm and below.
Other topics in this course include using database access commands, wire editing, metal fill, ECOs, and physical verification.
Learning Objectives
After completing this course, you will be able to:
- Import and floorplan a design
- Run placement and optimization using GigaPlace technology
- Plan, route and analyze the power
- Run timing analysis and debug results
- Create clock trees and concurrently run datapath optimization
- Run layer-aware timing- and power-driven optimization
- Run the slack-driven router with track-aware timing optimization
- Run global and detail routing for timing and signal integrity
- Debug routing violations
- Create and edit wires interactively
- Run ECOs on a design
- Address 20nm (and below) challenges as a result of Multi-Pattern Technology (MPT)
- Run design verification for geometry, connectivity, antenna and metal fill
- Run database access commands
- Run foundation flow scripts
- Run the Stylus Common UI to generate template implementation scripts
Software Used in This Course
- Innovus Implementation System
Software Release(s)
INNOVUS171 ISR1 (INVS17.11-s080_1)
Modules in this Course
- Innovus Implementation System Overview
- Design Import and Customizing the Innovus Implementation Environment
- Selecting and Highlighting Objects in the Design
- Floorplanning the Design
- Planning Power
- Routing Power with Special Route
- Running Placement Optimization
- Scan Optimization and Reordering
- Analyzing Route Feasibility with Early Global Route
- Extracting Parasitics and Analyzing Timing
- Multi-Mode Multi-Corner Analysis
- Optimizing and Closing Timing
- Implementing the Clock Tree with CCopt technology
- Detail Routing for Signal Integrity, Timing, and Design for Yield
- Debugging Routing
- Wire Editing
- Preventing and Fixing Signal Integrity Problems
- Metal Fill
- Verification
- Engineering Change Order (ECO)
- Writing Out a Design
- Challenges of Multi-Pattern Technology
- Innovus Database Access Commands
- Foundation Flow Scripts
- The Stylus Common UI
Audience
- CAD Engineers
- Chip Designers
- Physical Layout Designers
Prerequisites
You must have experience with or knowledge of the following:
- Design methodology
Related Courses
- Innovus Implementation System (Hierarchical)
- Innovus Clock Concurrent Technology for Clock Tree Synthesis
- Tempus Signoff Timing Analysis and Closure
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
“Everything was perfect. I'm very delighted I took part in it, it's incredibly useful to have a basic understanding of the whole flow. Lots of useful suggestions for further projects in regards of software questions. Very well described lab manual.”
Anze Jakos, Renishaw
“The course was very interesting and useful."
Yossi Shlush, Sandisk
“Everything was fine, perfect level of knowledge/experience.”
Yaroslav Ostrovsky, Microchip
„Overall useful course for a start in implementation - even for beginners“
Patrick Forster, Texas Instruments
"It was really well done and presented. Most of the topics are in line with what I am facing on a real challenging design. The training material was properly prepared by the trainers according to most of our requests, since most of us were already skilled on "basic" topics."
Lina Ferrari, STMicroelectronics
“I liked the pace of the course; the labs that followed each lecture/chapter and the chance to ask questions to the teacher. The course gave a good overview of the tools and some nice hands-on experience with the GUI. Very nice course and helpful instructor.”
Isac Jensen, Marvell
“Great intro to the tool, good instructor and learning environment.”
Michael Kesler