Quantus QRC Transistor-Level T3: Extracted View Flows and Advanced Features Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
15.2 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 1/2 day
Course Description
For classroom delivery, this course is taught as half day session (4 hours).
The course is designed to offer user-level experience on the next generation parasitic extraction solution from Cadence® – Quantus QRC. You first explore the documentation system and Cadence® online support and then explore the advanced node design solutions in Quantus QRC. You will analyze extraction challenges in FINFETs, 3DIC and Double Patterning (DPT) designs and respective Quantus QRC solutions. You will also learn how the extracted viewis integrated into the Virtuoso environment. You explore the Virtuoso® Parasitic Aware Designer (VPAD) flow, Parasitic Resimulation Flow and analog post-layout simulation flow in detail. Finally, you set up and perform EMIR analysis on Spectre/APS/MMSIM simulators in ADE environment.
In this course, you use the Virtuoso® Layout Suite and ADE environment. The Quantus QRC Extraction system is integrated into the Virtuoso menu bar for easy access.
Learning Objectives
After completing this course, you will be able to:
- Discuss Advanced Node Design and Extraction Challenges
- Assess benefits and challenges with designs involving DPTs and FinFETs
- See how Quantus™ QRC address Advanced node Extraction challenges
- Examine Quantus support for HPB Airgap Dielectric
- Explore Quantus QRC based extraction solutions for 3D-IC Designs with TSV
- Evaluate Comprehensive Quantus Integration to Virtuoso platform
- Review Virtuoso Parasitic-Aware Design (V-PAD) Flow for Extracted View
- Describe Parasitic Resimulation Flow with Spectre®/APS Simulators
- Analyze Transistor-Level EMIR Analysis Flow with Voltus™-Fi Custom Power Integrity Solution
- Explore Advanced features in Voltus-Fi-XL
Software Used in This Course
- Virtuoso Layout Suite
- Physical Verification System
- Quantus QRC Extraction
Software Release(s)
IC616, PVS15.1, EXT15.2
Modules in this Course
- Quantus QRC Advanced Node Features
- Post-Layout Simulation and EMIR Analysis
Audience
- Physical Verification and Extraction engineers who need to address parasitic issues in their advanced node designs
Prerequisites
You must have:
- Knowledge and experience with physical design, verification and extraction
- Familiarity with the Virtuoso® Layout Suite
- Familiarity with basic concepts of design parasitics, EMIR effects and simulation
Related Courses
- Quantus QRC Transistor-Level T1: Overview and Technology Setup
- Quantus QRC Transistor-Level T2: Parasitic Extraction
- Virtuoso Layout Design Basics
- Physical Verification System
- Assura Parasitic Extraction (RCX)
- Cadence QRC Techgen Developer
- Virtuoso Analog Design Environment
- High-Performance Simulation Using Spectre Simulators
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.