Xcelium Integrated Coverage Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
17.04 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 2 days
Course Description
This is an Engineer Explorer series course.The Engineer Explorer courses explore advanced topics.
This course explores Xcelium™ Integrated Coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of VHDL, Verilog and mixed-language designs. Not all coverage features are available with all languages. The course uses the Integrated Metrics Center for reporting and analysis and then discusses the collection and analysis of the following types of coverage:
- Code (branch, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog cover groups
- Control-oriented functional coverage using SystemVerilog assertions and the PSL
Learning Objectives
After completing this course, you will be able to:
- Effectively use the Xcelium integrated coverage with your VHDL, Verilog, and mixed-language designs
Software Used in This Course
- Xcelium Single Core
- vManager™ Linux Client
Software Release(s)
XCELIUM1704, MDV1704
Modules in this Course
- Introduction to Xcelium Integrated Coverage
- Identifying Coverage Types
- Identifying Code Coverage
- Defining Data Coverage with SystemVerilog Cover Groups
- Defining Control Coverage with SystemVerilog Assertions
- Defining Control Coverage with PSL Assertions
- Generating Coverage Data
- Analyzing Coverage Data Textually
- Analyzing Coverage Data Graphically
Audience
- Verification Engineers
Prerequisites
You must have:
- Familiarity with the VHDL or Verilog languages, and with design and design verification.
- Familiarity with SystemVerilog cover groups, and SystemVerilog and PSL assertions. This course reviews them only briefly.
Related Courses
- VHDL Language and Application
- Verilog Language and Application
- SystemVerilog for Design and Verification
- The Xcelium Simulator
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
"Great course, one of the best I attended until now (in terms of pure professional knowledge/experience). I liked the very well-structured and detailed material. The trainer also taught the material on very high-professional level and was very supportive during lab implementation.”
Sergey Dubinin, NXP Semiconductors
"Very good course and very effective instructor! He knows very well his subject and transmits it in a very pleasant manner. The mix lecture/lab is well done and the overall course is easy to digest."
Cedric Becu, STMicroelectronics
“Great course. Very practical and useful for us. I liked the great material and quality of labs.”
Dmitry Shushunov, NXP Semiconductors
"The course gave me a good insight to the possibilities of SystemVerilog. Also with only small knowledge of the Verilog language it was easy for me to follow the course objectives and do the labs."
Sebastian Raschbacher, Freescale Semiconductor
"The course was very helpful for me."
Zeynep Dincer Vural, STMicorelectronics
“This course was really helpful and I have improved my knowledge with the indepth introduction & explanation to the subject.”
Leela Thimmaiah, Technical University Darmstadt