Perspec System Verifier – Basic Training
Date | Version | Country | Location | |
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Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
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15.2 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Course Description
This training course introduces you to the Cadence® Perspec™ System Verifier. The Perspec System Verifier is a software-driven system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for complex SoC-level use cases, creating coverage-driven automation of system use-case generation, and shrinking the time required to reproduce, debug, and fix complex SoC-level bugs.
Learning Objectives
After completing this course, you will be able to:
- Explain the Perspec System Verifier (SVR) purpose and usage
- Model components for the Perspec SVR
- Compose scenarios with the Perspec SVR
- Generate and examine coverage metrics from the Perspec SVR
Software Used in This Course
- Incisive® Enterprise Simulator XL
- Perspec Composer/Solver
- Perspec Cadence Simulation Platform Runtime
Software Release(s)
INCISIVE152
Modules in this Course
- Perspec System Verifier Introduction
- Perspec System Verifier Component Modeling Basics
- Perspec System Verifier Scenario Composition Basics
- Perspec System Verifier Coverage Metrics Generation and Analysis
Audience
- SoC verification personnel
Prerequisites
You must have experience with or knowledge of the following:
- A high-level verification language
- System-level digital verification
Related Courses
- C++ Language Fundamentals for Design and Verification
- SystemVerilog for Design and Verification
- Incisive SystemC, VHDL, and Verilog Simulation
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Course ID: 86213