Virtuoso ADE Verifier Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Length : 1 day
Course Description
In this course, you learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool, which is a new feature in IC 617. You can effectively manage and verify requirements of design blocks owned by multiple engineers. You can use multiple design flow approaches to meet your verification specs. This course emphasizes on the top-down flow. Hierarchical design requirements are mapped to implementation tests in a single cockpit. The implementations are test setups coming in from maestro cellviews, which can be simulated to gather results and view the detailed verification status.
Learning Objectives
After completing this course, you will be able to:
- Define the verification requirements of your design
- Map your design implementations (tests defined in maestro cellviews) to your requirements
- Set up and run the Virtuoso ADE Verifier
- Debug the verification status of individual requirements
- Analyze the overall verification status of the entire design verification project
- Print verification result
- Set up the verification project for a multi-user environment with multiple requirement owners
- Create batch-based verification regression runs
Software Used in This Course
- Virtuoso ADE Verifier
- Virtuoso ADE Assembler
- Spectre Circuit Simulator
Software Release(s)
IC617 ISR17, SPECTRE17.1
Modules in this Course
- The Virtuoso Design Environment (Optional)
- Invoking the Virtuoso ADE Verifier
Adding Requirements and Implementations
Mapping and Running Simulations
Managing Verification Results
- Managing Multiple Requirement Owners
Audience
- Analog mixed-signal designers performing requirements-driven verification of analog designs
- Verification Leads
- Project Managers
Prerequisites
Before taking this course, you need to have:
- An understanding of analog design simulation and verification methodologies
- Some exposure to the Virtuoso® IC 6.1.7 software from Cadence®
Or you must have completed one of the following courses:
- Virtuoso ADE Assembler S1: Introducing the Assembler Environment
- Virtuoso ADE Explorer S1: Set Up and Run Analog Simulations Using the Spectre Simulator
Related Courses
- Virtuoso ADE Explorer (Sections 1 to 4)
- Virtuoso ADE Assembler (Sections 1 to 3)
- Variation Analysis Using the Virtuoso ADE Assembler
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
"It is already my third course with this presenter(…)as in previous cases my impressions are only positive, it is really helpful and improving my designing skills."
Ludek Pantucek, ONSemiconductor