Tensilica Xtensa Processor Interfaces Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
7.0 | Online | ENROLL |
6.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 1 day
Course Description
This four hour course provides information about Tensilica® processor technology and how to use Tensilica product deliverables for your SoC design. You explore topics regarding the Xtensa® processor interfaces. This includes the following interfaces:
- Processor Interface (PIF)
- Local memory interfaces
- TIE interfaces
- Debug and trace interfaces
- Control interfaces
- Power shut-off interface
The solid fundamentals taught in this course enable you to quickly become productive in the use of Xtensa processors for your SoC design.
Learning Objectives
After completing this course, you will be able to:
- Understand Xtensa interfaces in depth
- Discuss use case examples of each interface
- Design your SoC with the best use of Xtensa interfaces
Software Used in This Course
- Xtensa Software Tools Release RG-2016.3
Software Release(s)
- RG-2016.4
Modules in this Course
- Xtensa Bus Interface (PIF)
- AMBA Bridge Support
- Xtensa Local Memory Interfaces
- TIE Interfaces
- Debug and Trace Interfaces
- System Control Interfaces
- Power Shut-Off
Audience
- SoC architects designing systems with Xtensa processors
- Architects/Designers configuring Xtensa processors for a specific application
- Design verification engineers
Prerequisites
You must have experience with or knowledge of the following:
- Basic microprocessor architecture
- RTL design for hardware engineers
And you must have completed the following course:
System Requirements for Online Courses
- For system requirements click here
- Cadence software as listed above installed and licensed
Related Courses
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Course ID: 86066