Broadcom
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Overview
AI-Driven Automated Approach to Chip Design—Delivering Improved PPA and Productivity
Engineering teams are overloaded and need help to keep up with the ever-increasing demands on chip designs. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, artificial intelligence (AI)-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus will intelligently optimize the design to meet these power, performance, and area (PPA) goals in a completely automated way.
By adopting Cadence Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. Additionally, through the Cadence Cerebrus full-flow reinforcement learning technology and large language model (LLM) capabilities in Cadence.AI Generative AI Platform, engineering team productivity is greatly improved.
Key Benefits
Better PPA
Chip design flow from RTL to GDS, automatically optimized for PPA
Improved Productivity
Engineers can quickly optimize flows for many blocks concurrently and use that knowledge for the next design
Scalability
Efficient distributed compute AI technology, also enabled for cloud
Easy to Use
Designer cockpit allows interactive results analysis, so engineers always have control
Features
Full-Flow Optimization that Boosts Productivity and Time to Market
Customer Success
Learn how customers use Cadence Cerebrus to optimize PPA while automating processes.
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Customer Stories
See What Customers Have to Say
We use a wide portfolio of Cadence solutions across our business units, and we have seen outstanding PPA improvements from the use of the AI capabilities of Cadence Cerebrus.
Yuan Xing Lee, Broadcom
With the powerful combination of Cadence Cerebrus and the complete Cadence digital full flow, our team was able to automate processes that were previously manual, which saved us time and helped us achieve our PPA goals.
Tim Mamtora, Imagination Technologies
On an SoC block, the Cadence Cerebrus floorplan optimization feature shrunk the die area by 5% and reduced power by more than 6%.
MediaTek
By deploying and optimizing Cadence Cerebrus to fit all our unique needs, we’ve had many notable design wins already. On an advanced-node CPU design, we experienced better performance with a 75% improvement in total negative slack (TNS).
Toshonori Inoshita, Renesas
Resources
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