Virtuoso Schematic Editor Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
IC6.1.7 | Online | ENROLL |
IC6.1.5 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 2 days
Course Description
In the Virtuoso® Schematic Editor course, you learn to create and edit schematics for use with the suite of Cadence® simulation and layout tools. You access both the L and XL tool suite capabilities. You place instances, wire schematics, use hierarchical design concepts for multi-level schematics. You then use the Verilog In and SPICE In translators to generate netlists and symbols.
You also create the circuit netlist and run a simulation.
In Schematics XL, you add design rules using the Constraint Editor and Circuit Prospector assistants. In addition, you create inherited connections, and generate layout instances from the schematic.
Learning Objectives
After completing this course, you will be able to:
- Create schematics, symbols, libraries, and components for use in your designs
- Use bindkeys to increase your efficiency and automate repetitive tasks
- Edit component properties and configurations
- Understand flat and hierarchical schematics
- Create netlists and run simulations
- Run Verilog In and SPICE In to generate netlists and schematic symbols
- Add design constraints in schematics for use in the layout
- Establish inherited connections to allow for variables to establish design properties on hierarchical instances
Software Used in This Course
- Virtuoso Schematic Editor L
- Virtuoso Analog Design Environment L
- Virtuoso Schematic Editor XL
Software Release(s)
IC 6.1.7 ISR 10 and SPECTRE 16.1
Modules in this Course
- Introduction to the Virtuoso Design Environment
- Capturing Design Schematics
- Generating Symbols for the Schematics
- Navigating the Design Hierarchy
- Advanced Schematic Capture Techniques
- Creating Constraints in a Schematic
- Working with Inherited Connections
The Appendix section contains a discussion on using the Power Intent Export Assistant in Schematics XL.
Audience
- Analog/Mixed-Signal IC Designers
- Analog Designers
- Analog IC Designers
- Chip Designers
- Custom Circuit Designers
- Design Engineers
- IC Designers
- RF Designers
Prerequisites
This is a basic level course to start creating designs in the Virtuoso Design Environment. There are no prerequisites for this class.
Related Courses
- Virtuoso Analog Design Environment
- Spectre Simulations Using Virtuoso ADE
- Virtuoso Analog Simulation Techniques
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.