SystemVerilog Accelerated Verification with UVM1.2 Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Length : 5 days
Course Description
Universal Verification Methodology (UVM) is the IEEE1800.1 class-based verification library and reuse methodology for SystemVerilog. The UVM class library provides the basic building blocks for creating verification data and components. The UVM methodology enables engineers to quickly develop powerful, reusable, and scalable object-oriented verification environments.
The course begins with an optional short review of SystemVerilog class constructs and an overview of object-oriented concepts and features.
The majority of the course describes a methodology for using the building blocks of the UVM class library to create a configurable, reusable UVM Verification Component (UVC) based on a standard architecture. Then you learn how to combine multiple UVCs into a flexible, powerful verification environment with scoreboarding and register modeling.
This version of the class teaches a methodology compatible with hardware acceleration. See the video "Future-Proof Your UVM Environments with Acceleration Optimization" for more information.
Learning Objectives
After completing this course, you will be able to:
- Understand the features and capabilities of the UVM class library for SystemVerilog
- Create and configure reusable, scalable, and robust UVM Verification Componenets (UVSs)
- Combine multiple UVCs into a complete verification environment
Software Used in This Course
- Incisive Enterprise Simulator XL
Software Release(s)
INCISIVE152
Modules in this Course
Day 1 – Section 1: Essential SystemVerilog and Object-Oriented Design for UVM
- Review of basic SystemVerilog classes
- Polymorphism and casting
- Virtual classes and methods
- Developing robust class methods
- Class-based component hierarchy
Days 2-4 – Section 2: UVM Verification Environment
- Introduction to UVM Methodology and Universal Verification Component (UVC) structure
- Overview of the Router Lab Project
- Stimulus Modeling
- Declaring data items
- Field automation and data operations (copy, clone, print, etc.)
- Simulation Phases
- Standard and run-time phasing
- Creating a Simple Environment
- UVM component classes
- Structure of a simple environment
- Messaging
- Packaging and directory structures
- Test Classes
- Test selection
- Configuration
- Configuration database (uvm_config_db)
- How configuration works, with rules, examples and debugging
- set_config method calls (deprecated in UVM1.2)
- Type Overrides and the Factory
- Constraint layering and behavior modification
- Factories
- Type and instance overrides
- UVM Sequences
- Sequence structure
- uvm_do macros
- Alternatives to uvm_do macros
- Nested sequences and sequence properties
- Objection mechanism for stopping simulation
- Objection changes in UVM1.2
- Sequence selection
- Connecting to a DUT
- The testbench layer
- Virtual SystemVerilog interfaces
- Assigning interfaces using the configuration database
- Interface and Module UVCs
- Integrating multiple UVCs
- UVCs with multiple agents
- Configuration objects
- Multichannel Sequences (virtual sequences)
- Virtual sequencers
- Defining virtual sequences
- Building a Scoreboard
- Scoreboard requirements and considerations
- Connecting components with TLM analysis interfaces
Day 5 – Section 3: Further UVM
- Transaction-Level Modeling (TLM)
- Concepts and terminology
- Simple, unidirectional connections (put, get, peek)
- More complex connections (transport, analysis)
- TLM FIFO connections
- Hierarchical connections with export
- TLM2
- Functional Coverage Modeling
- Coverage-driven verification overview
- Coverage considerations in a UVC
- Introduction to Register Modeling
- Overview of the purpose and structure of register modeling
- Generation of a register model
- Integration into an environment
- Simulation using built-in and user-defined register sequences
- Conclusions
Lab Exercises
Lab exercises are structured around verification of a real-life router design. The lab sessions include:
- Creating simple stimuli
- Universal Verification Component (UVC) architecture
- Factories and configuration control
- Sequences
- Integrating multiple UVCs
- Writing multichannel and system-level tests
- Building a scoreboard
- Functional coverage
- Register modeling of a standalone design
Audience
- Design engineers
- Verification engineers
Prerequisites
You must have experience with or knowledge of the SystemVerilog Language, specifically:
- Declaring and use of SystemVerilog class instances
- Static methods and properties
- Inheritance and composite classes
- Randomization and constraint of class properties
Or you must have completed one of the following courses:
Related Courses
- SystemVerilog for Design and Verification
- SystemVerilog for Verification
- SystemVerilog Advanced Register Verification with UVM
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"Perfect. It was a very useful and comprehensive training, with a great teacher."
Daniel Krakov, Sandisk
“I'm very glad I took this course. It completely answered my demands.”
Eran Shalev, Intel
"The course curriculum was built very good, especially the combination of the theory and the labs. The teacher was really great(...)nothing to improve."
Shaul Kerman, Western Digital Corporation
"Great instructor, good atmosphere, well-built course!"
Eyal Falk, Intel