Genus Synthesis Solution with Stylus Common UI Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
17.2 | Online | ENROLL |
17.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Course Description
In this course, you learn about the features of the Cadence® Genus™ Synthesis Solution with Stylus Common UI with next generation synthesis capabilities (massively parallel, tight correlation, RTL design focus and Architecture level PPA) and how SoC design productivity gap is filled by Genus. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, run physical synthesis, optimize for low-power structures, analyze DFT (design for testability) constraints, and interface with other tools in Genus Stylus CUI. You will be able to identify the steps required to perform logic optimization for digital design and generate various input and output files.
You also learn how to run complete synthesis flow on a design with the given specifications and optimize it for area, timing, and power using Stylus Common UI. You will learn to query the design database and set attributes for synthesis flow in Genus Stylus CUI. You explore Mulit Mode Multi Corner Synthesis Flow in Genus. You also identify Flowkit and Unified Metrics capabilities.
Note: This course is based on the Stylus Common UI which is limited-release in Genus Synthesis Solution 17.1. Please consult with your Cadence AE before deciding to taking this course or the course called Genus Synthesis Solution which is based on the Legacy UI and not on the Stylus UI.Learning Objectives
- Explore the features of the Genus and Stylus Common User Interface
- Apply the recommended synthesis flow using the Cadence Genus Synthesis Solution
- Explore MMMC and how to set up and update the MMMC configuration of a design
- Debug design scenarios
- Use the extended datapath features
- Optimize designs using the physical synthesis flow
- Analyze and synthesize the design for low-power structures
- Constrain the design for testability (DFT)
- Identify the interface to Conformal® equivalence checker and other tools
- Explore Flowkit and Unified Metrics
Software Used in This Course
- Genus Synthesis Solution
Software Release(s)
Genus 17.2
Modules in this Course
Audience
Prerequisites
You must have experience with or knowledge of the following:
- Any HDL such as Verilog (recommended) or VHDL
- Synthesis and ASIC design flow basics
- Static Timing Analysis
Or you must have completed the following courses:
Related Courses
- Genus Synthesis Solution
- Logic Equivalence Checking with Conformal EC
- Innovus Digital Implementation (Block)
- Innovus Digital Implementation (Hierarchical)
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.