Tempus Signoff Timing Analysis and Closure Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
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17.2 | Online | ENROLL |
16.2 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 2 days
Course Description
This course is a detailed exploration of the timing and signal integrity analysis capabilities of the Tempus™ Timing Signoff Solution. In this course, you analyze a design for static timing and signal integrity issues that are inherent in advanced process nodes with feature sizes 90nm and below. You also run signoff timing analysis to analyze the timing issues on large designs and fix timing issues using the Innovus™ Implementation System.
Learning Objectives
After completing this course, you will be able to:
- Identify timing analysis data requirements and import single corner designs, multimode multicorner (MMMC) designs, and multisupply voltage (MSV) designs
- Run parallel processing techniques like distributed MMMC and Distributed Static Timing Analysis (DSTA)
- Identify and apply timing debug techniques using the Global Timing Debug interface
- Analyze a design for timing combined with signal integrity (SI)
- Run ECO analysis and timing closure flow between the Innovus Implementation and Tempus Signoff tools
Software Used in This Course
- Tempus Timing Signoff Solution
- Innovus Implementation System
Software Release(s)
SSV172, INNOVUS171
Modules in this Course
- Introduction to the Tempus Timing Signoff Solution
- Design Import and Tool Flow
- Preparing for Timing Analysis
- Timing Debug
- Crosstalk Analysis
- Parallel Processing
- MMMC Signoff ECO Flow
Audience
- Digital IC Designers
- IC Designers
- Place-and-Route Designers
Prerequisites
You must have experience with or knowledge of the following:
- Cadence physical design tools
- Static Timing Analysis
Related Courses
Course ID: 82147