Innovus Block Implementation with Stylus Common UI Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Length: 3 days
Course Description
Note: This course is based on the Stylus Common UI, which is a limited release in Innovus™ 17.1. Please consult with your Cadence AE before deciding to take this course instead of the course called Innovus Implementation System (Block), which is based on the default UI and not on the Stylus UI.
In this course, you learn how to use the Innovus Implementation System software using the Stylus Common User Interface (UI) to achieve the best power, performance and area (PPA) for your design. You learn several techniques for floorplanning and placement using the GigaPlace™ solver-based placement while implementing timing closure strategies with a multi-threaded, layer-aware timing and power-driven optimization engine to reduce dynamic and leakage power. You will learn how to set up and run the concurrent clock and datapath optimization engine to enhance cross-corner variability and boost performance with reduced power.
You run the slack-driven router with track-aware timing optimization which enables you to achieve the multiple objectives that are a part of today's design requirements. You will learn how to diagnose and fix routing violations as well as explore challenges and solutions for design implementation in nodes that are 20nm and below.
Other topics in this course include using database access commands, wire editing, metal fill, ECOs and physical verification.
Learning Objectives
After completing this course, you will be able to:
- Import and floorplan a design
- Run timing analysis and debug results
- Create clock trees and concurrently run datapath optimization
- Run layer-aware timing- and power-driven optimization
- Run the slack-driven router with track-aware timing optimization
- Run global and detail routing for timing and signal integrity
- Debug routing violations
- Create and edit wires interactively
- Run ECOs on a design
- Address 20nm (and below) challenges as a result of Multi-Pattern Technology (MPT)
- Run design verification for geometry, connectivity, antenna and metal fill
- Run database access commands
- Run the Stylus Common UI flow generation tool to automatically implementation scripts
Software Used in This Course
- Innovus Implementation System
Software Release(s)
INNOVUS171
Modules in this Course
- Innovus Implementation System Overview
- Design Import and Customizing the Innovus Implementation Environment
- Selecting and Highlighting Objects in the Design
- Floorplanning the Design
- Planning Power
- Routing Power with Special Route
- Running Placement Optimization
- Scan Optimization and Reordering
- Analyzing Route Feasibility with Early Global Route
- Extracting Parasitics and Analyzing Timing
- Multi-Mode Multi-Corner Analysis
- Optimizing and Closing Timing
- Implementing the Clock Tree with CCopt technology
- Detail Routing for Signal Integrity, Timing, and Design for Yield
- Debugging Routing
- Wire Editing
- Preventing and Fixing Signal Integrity Problems
- Metal Fill
- Verification
- Engineering Change Order (ECO)
- Writing Out a Design
- Challenges of Multi-Pattern Technology
- Innovus Database Access Commands
- Stylus Flow Generation
Audience
- CAD Engineers
- Chip Designers
- Physical Layout Designers
Prerequisites
You must have experience with or knowledge of the following:
- Design methodology
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.