SystemVerilog for Design and Verification Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
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20.3 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 5 days
Course Description
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course gives you an in-depth introduction to the main SystemVerilog enhancements to the Verilog® hardware description language (HDL), discusses the benefits of the new features, and demonstrates how design and verification can be more efficient and effective when using SystemVerilog constructs.
The course breaks down into two modules. The Design module examines improvements for RTL design and synthesis; and the Verification module explores verification enhancements such as object-oriented design, assertions and randomization.
Learning Objectives
After completing this course you will be able to:
- Understand and use the SystemVerilog RTL design and synthesis features, including new data types, literals, procedural blocks, statements, and operators; relaxation of Verilog language rules; fixes for synthesis issues; enhancements to tasks and functions; new hierarchy and connectivity features, and interfaces.
- Appreciate and apply the SystemVerilog verification features, including classes, constrained random stimulus, coverage, strings, queues and dynamic arrays, and learn how to utilize these features for more effective and efficient verification.
Software Used in This Course
- Incisive Enterprise Simulator XL
Software Release(s)
- Incisive 13.1
Course Agenda
Days 1-2: SystemVerilog for Design
The first two days cover fundamental language enhancements and the SystemVerilog features aimed at RTL design, and form an essential base for exploring Verification features.
- SystemVerilog Overview
- Standard Data Types and Literals
- Procedures and Procedural Statements
- Operators
- User-Defined Data Types
- Hierarchy and Connectivity
- Static Arrays
- Tasks and Functions
- Interfaces
- Conclusions and Next Steps
Days 3-5: SystemVerilog for Verification
The last three days examine Verification features of SystemVerilog in depth.
- Verification Overview
- Clocking Blocks
- Scope-Based (Variable) Randomization
- Basic Classes and Object-Oriented Design
- Virtuality and Polymorphism
- Class-Based Randomization
- Virtual Interfaces
- Covergroup Functional coverage
- Queues and Dynamic and Associative Arrays
- Assertion-Based Verification (ABV)
- Introduction to SystemVerilog Assertions (SVA)
- Direct Programming Interface (DPI)
- Interprocess Synchronization
- Conclusions and Next Steps
Appendices
- Verilog2001 Review
- SystemVerilog Event Scheduler
- Programs
- Miscellaneous Features
Audience
Prerequisites
You must have:
Related Courses
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"Great course, one of the best I attended until now (in terms of pure professional knowledge/experience). I liked the very well-structured and detailed material. The trainer also taught the material on very high-professional level and was very supportive during lab implementation.”
Sergey Dubinin, NXP Semiconductors
"Very good course and very effective instructor! He knows very well his subject and transmits it in a very pleasant manner. The mix lecture/lab is well done and the overall course is easy to digest."
Cedric Becu, STMicroelectronics
“Great course. Very practical and useful for us. I liked the great material and quality of labs.”
Dmitry Shushunov, NXP Semiconductors
"The course gave me a good insight to the possibilities of SystemVerilog. Also with only small knowledge of the Verilog language it was easy for me to follow the course objectives and do the labs."
Sebastian Raschbacher, Freescale Semiconductor
"The course was very helpful for me."
Zeynep Dincer Vural, STMicorelectronics
“This course was really helpful and I have improved my knowledge with the indepth introduction & explanation to the subject.”
Leela Thimmaiah, Technical University Darmstadt