Tensilica Processor Fundamentals Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
7.4 | Online | ENROLL |
6.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 2 days
Course Description
This course provides basic information about Tensilica® processor technology and how to use Tensilica product deliverables for your SoC design. You explore topics in processor architecture and the configurable options of the Xtensa® LX series processors. You practice working with the Xplorer Integrated Development Environment (IDE), working with Tensilica software tools, and programming Xtensa processors in the labs that are part of this course. You also program Xtensa processors with application-specific instructions added by using the Tensilica Instruction Extension (TIE) language.
Emulation of a Tensilica processor is discussed and demonstrated. The solid fundamentals taught in this course enable you to quickly become productive in the use of Xtensa processors for your SoC design.
Learning Objectives
After completing this course, you will be able to:
- Use Xtensa Xplorer (IDE) for software development
- Write, optimize, and debug C/C++ code for any Xtensa processor core
- Understand Xtensa processor architecture features and their impact on performance
- Configure an Xtensa processor suitable for your application
- Customize your application’s memory map to match your target system
- Program Xtensa processors that have TIE extensions
- Emulate and debug Xtensa processor on an FPGA or other emulation platform
Software Used in This Course
- Xtensa Software Tools Release RG-2016.4
Software Release(s)
RG-2016.4
Modules in this Course
Tensilica Processor Architecture
- Processor Architecture Basics
- Xtensa-Specific Instruction Architecture Features
- Generating a New Xtensa Core
- AR Register File and the Application Binary Interface
- Xtensa-Specific Local Memory Architecture
- Xtensa-Specific System Memory Interface
- Xtensa TIE Interfaces
- Xtensa Exception and Interrupt Architecture
- Power Saving Features
Programming Cores with Tensilica Instruction Extensions
- Introduction to Tensilica Instruction Extensions
- Writing C/C++ Code for Instruction Extensions
- Understanding Compiled Code
- Simulating C/C++ Code with TIE
Developing Software forXtensa Processors
- Introducing Xtensa Xplorer (Finding help and documentation, relationship between projects, configurations, and tools)
- Lab: Installation and licensing; getting help and information; about your processor; a first program
- Working with Projects and Build Targets (Xplorer perspectives and build targets; setting build options, creating projects)
- Lab: Creating projects with QuickStart Wizard; linking folders; the active set; running your program
- Running and Profiling with Xplorer (Setting simulator options, running and profiling, analyzing profile data)
- Lab: Installing sample code; perspectives; benchmarking; varying test runs; build targets; profiling
- Debugging your Code (Using Debug perspective, controlling execution, tracing)
- Lab: Debugging your code
- Command-Line Environment (Configuring and using Xtensa tools from the command line)
- Lab: Command lines; compiling, running, debugging and profiling your application; varying processors
- Introduction to Linker Support Packages (Concepts, placing your code in specific memory)
- LSP Advanced Topics (Memory map editor, structure of an LSP, generating linker scripts)
- Lab: importing; memory maps; identifying sections; running; modifying a memory map; moving stack/heap
- Hardware Exceptions and Interrupts (basic behavior, interrupt priorities, XTOS handler responsibilities)
- XTOS and HAL (writing XTOS applications, interrupt handlers in XTOS, HAL timers)
- Lab: Importing; understanding interrupt and timer code; writing the main function; compiling and simulating
Xtensa Debug/Trace & Introduction to Hardware Deliverables
- Building Target Software for Real Hardware
- Configuration Options for Hardware Debug and Trace
- Single and Multiple-Core Debug Session Demonstrations
- Debug Monitor (Xmon)
- Xtensa Hardware Package
Audience
- SoC architects designing systems with Xtensa processors
- Architects/Designers configuring Xtensa processors for a specific application
- Software developers programming Xtensa processors
- Other software/hardware engineers working extensively with Xtensa processors
Prerequisites
You must have experience with or knowledge of the following:
- Basic microprocessor architecture
- Programming in C/C++
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
“The course met my expectations. A practical course on implementing the physical prototype of a Tensilica Processor in an FPGA board. The support is good and it is easy to enroll and access the courses.”
Jones M.A. Da Silva, Ruhr University Bochum