Quantus QRC Transistor-Level T1: Overview and Technology Setup Training
Date | Version | Country | Location | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Version | Region | |
---|---|---|
15.2 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length : 1/2 day
Course Description
For classroom delivery, this course is taught as half day session (4 hours).The course is designed to offer user-level experience on the next generation parasitic extraction solution from Cadence® – Quantus QRC. You explore the documentation system and Cadence online support. You will learn the parasitic extraction challenges in design closure and Quantus QRC solutions to tackle it. You will also see how Quantus QRC extraction fits into the design flow and how to set up the extraction environment. You will analyze Quantus-QRC technology directory structure, explore extraction features and check out modes – GUI and command-line – of effectively extracting parasitic resistance, capacitance and inductance.
In this course, you use the Virtuoso® Layout Suite. The Quantus QRC Extraction system is integrated into the Virtuoso menu bar for easy access.
Learning Objectives
After completing this course, you will be able to:
- Assess Parasitic Extraction Challenges in design closure
- Elicit Quantus QRC extraction features and solutions
- Apply Quantus™ QRC extraction into the design flow
- Set up the Quantus QRC extraction environment – in GUI and Batch modes
- Analyze Quantus QRC Technology Directory Files and Setup
- Overview Quantus Techfile creation through Techgen Flow
- Compare Single vs. Multi-Corner extraction
- Set up and create Extracted View with control files
- Use distributed processing (parallelism) to speed up extraction
Software Used in This Course
- Virtuoso Layout Suite
- Physical Verification System
- Quantus QRC Extraction
Software Release(s)
IC616, PVS15.1, EXT15.2
Modules in this Course
- Overview of Quantus QRC Extraction
- Quantus QRC Technology Setup
Audience
- Physical Verification and Extraction Designers who need to address parasitic issues in their design
Prerequisites
You must have:
- Knowledge and experience with physical design, verification and extraction
- Familiarity with the Virtuoso® Layout Suite
- Familiarity with basic concepts of design parasitics, EMIR effects and simulation
Related Courses
- Quantus QRC Transistor-Level T2: Parasitic Extraction
- Quantus QRC Transistor-Level T3: Extracted View Flows and Advanced Features
- Virtuoso Layout Design Basics
- Physical Verification System
- Assura Parasitic Extraction (RCX)
- Cadence QRC Techgen Developer
- Virtuoso Analog Design Environment
- High-Performance Simulation Using Spectre Simulators
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.