Overview

Best-in-class UCIe Verification IP for your IP, SoC, and system-level design testing.

The Cadence Verification IP (VIP) for Universal Chiplet Interconnect Express (UCIe) is designed for easy integration in test benches at the IP, system-on-chip (SoC), and system level. The VIP for UCIe runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality.

UCIe Diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM
  • UVM building blocks
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker and Waveform debugger for efficient debugging
  • SystemVerilog coverage model
  • Trace for issue replay

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Layer
  • Logical PHY
  • D2D Adapter
  • Protocol

Mode
  • Streaming
  • PCIe over UCIe

Interfaces
  • FDI (FLIT data interface connecting Protocol layer with D2D Adapter layer)
  • RDI (Raw data interface connecting D2D Adapter layer with PHY layer)
  • UCIe PHY Mainband and Sideband

Passive monitor
  • UCIe link monitor

Pseudo Protocol port
  • API interface to inject user-defined FLITs in Protocol layer

Pseudo FDI port
  • API interface to inject user-defined Sideband and Mainband packets (FLITs) in D2D Adapter layer, bypassing FDI

Psuedo RDI port
  • API interface to inject user-defined Sideband and Mainband packets in PHY layer (bypassing RDI)

FDI/RDI Mb Data Width
  • 128, 256, 512, 1024, 2048 bits

FDI/RDI Sb Data Width
  • 8 bits

Module
  • Single

PHY Max Link Speed
  • 4, 8, 12, 16, 24, 32GT/s

PHY Training
  • Sideband training
  • Mainband training
    • Data to clock point
    • Repair clock
    • Repair val
    • Retrain

PHY Features*
  • Sideband link repair
  • Sideband Data/clock repair
  • Data lane repair
  • Dynamic clock gating
  • Clock and track lane repair
  • Lane reversal

Model Capabilities

 <
  • Standalone layer, Partial stack, Full-stack
  • LTSM training bypass
  • Scrambler bypass
  • Configurable number of D2C training attempts and pattern count
  • Debug ports
  • Packet IDs for packet tracking within a layer

Package

 <
  • Standard (16 lanes)
  • Advanced (64 lanes)

FSMs

 <
  • PHY LTSM
  • PHY RDI SSM
  • D2D Adapter RDI SSM
  • D2D Adapter FDI LSMs
  • Protocol FDI LSMs

Registers

 <
  • Spec defined (DVSEC, Protocol, Adapter and PHY) registers
  • Model registers

Error Injections

 <
  • Modifiable transaction fields through Callbacks
  • PHY: Valid framing error
Features coming in future releases
  • Layered CXL over UCIe
  • Multi-module PHY
  • Multi-stack
  • Power management: PM states for FDI LSM, RDI SSM and LTSM

Simulation Test Suite

UCIe VIP has a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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