Best-in-class Ethernet Verification IP for your IP, SoC, and system-level design testing

The Cadence Verification IP (VIP) for Ethernet 5G Networking provides a mature, highly capable compliance verification solution for the 5G network protocol stack incorporating bus functional model (BFM) and integrated protocol checkers and coverage. The VIP for Ethernet 5G Networking is designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels, helping to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet 5G Networking is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Ethernet 5G diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation, error injection
  • Transaction Tracker: Configurable tracking of all the transactions on the channels
  • SystemVerilog coverage infrastructure for extendable coverage
  • Predefined protocol checkers to evaluate the compliance of the DUT model to protocol requirement

Key Features

The following table shows key features from the specifications that are implemented in the VIP:

Feature Name

Description

SyncE

  • Supports clock generation from the transmit side
  • Supports Hold-off and Wait-to-restore feature
  • Support for 25G speed with serial interface

eCPRI

  • Supports all 12 message types of eCPRI
  • Supports packet generation on the transmit side and extraction on the receive side
  • Supports transmission of eCPRI over IET
  • Supports up to 800G speed
IPsec
  • Supports ESP frame packing/unpacking in Tunnel mode for Ipv4/Ipv6 packets (RFC-4303)
  • Supports AES-GCM algorithm for encryption/decryption with 128/256-bit key (RFC-4106)
  • Supports Null Encryption Algorithm (RFC-2410)
  • Supports SPD and SAD databases (RFC-4301)

仿真测试集合

VIP 附带一个场景测试集合,可轻松评估和部署 VIP

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