Overview

JTAG Verification IP for your IP, SoC, and system-level design testing.

The Cadence® JTAG Verification IP provides support for the JTAG protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. JTAG VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

JTAG diagram

Product Highlights

  • Constrained-random traffic generation for both manager and subordinate
  • Comprehensive checkers for specification compliance.
  • Coverage: Monitors, checks, and collects coverage on bus traffic
  • Error injection support
  • Transaction tracker: Configurable tracking of all the transactions

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Multiple subordinates
  • Supports multiple subordinates. Parallel/serial configuration is supported

Instructions
  • Supports all standard defined instructions

Clamp
  • Optional instruction CLAMP is supported

High Z
  • Optional instruction HIGHZ is supported

Extest
  • Optional instruction EXTEST is supported

Extest Pulse
  • Optional instruction EXTEST_PULSE is supported (from 1149.6 standard)

Extest Train
  • Optional instruction EXTEST_TRAIN is supported (from 1149.6 standard)

Instruction Length
  • Instruction length is configurable

Instruction Codes
  • Instruction codes are configurable

仿真测试集合

VIP 附带一个场景测试集合，可轻松评估和部署 VIP

如需更多信息请联系我们

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