Best-in-class Ethernet Verification IP for your IP, SoC, and system-level design testing. Mature and highly capable compliance verification solution.
Incorporating the latest protocol updates, the mature and comprehensive Cadence Verification IP (VIP) for the Ethernet 1.6T protocol provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels, the VIP for Ethernet 1.6T helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet 1.6T runs on all major simulators and supports SystemVerilog and e verification languages with associated methodologies, including the Universal Verification Methodology (UVM).
The VIP for Ethernet 1.6T enables verification of Ethernet interfaces in MAC standalone and full-stack mode for speeds up to 1.6Tbps at different levels:
XMII level: Between MAC and PHY
PCS, PMA, PMD levels: Between PHY sub-layers
TX/RX Stations: Between link partners
Supported specifications:Ethernet Technology Consortium r1.0, IEEE 802.3-2018, IEEE 802.3cd-2018 50G, IEEE 802.3ck 100G, IEEE 802.3by 25G, USXGMII Cisco spec version 2.12 for multi-port and 2.2 for a single port, USGMII Cisco spec version 3.0, Proposed Draft Version opsasnick_3dj_01a_2303, gustlin_3dj_01b_230206, ran_3dj_01a_2303
Product Highlights
Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
Predefined protocol checkers to evaluate the compliance of the DUT model with protocol requirements
Callbacks access at multiple TX and RX queue points for scoreboarding, data manipulation, and error injection
Packet tracker creation for easy debugging
Extensive SystemVerilog coverage model with infrastructure for extension
Key Features
The following table shows key features from the specifications that are implemented in the VIP:
Feature Name
Descriptions
1.6Tbps Interfaces
1.6Tbps Ethernet interfaces based on Ethernet Technology Consortium supports:
1.6TMII
1.6TBase-R Dual-PCS 16 lanes (100Gb/s)
RS FEC (544,514)
PMA (1:1 Mux, 2:1 Mux) - 16x100GPL, 8x200GPL
Multi-lane distribution (MLD) to distribute data from a single Media Access Control (MAC) channel across 16 PCS lanes
Compliance mode
Full duplex operation
Internal and external clock mode
PAM4 modulation scheme
800Gbps Interfaces
800Gbps Ethernet interfaces based on Ethernet Technology Consortium supports:
800GMII
800GBase-R Dual-PCS 32 lanes (25Gb/s)
RS FEC (544,514)
PMA (4:1 Mux) - 8x106.25G, 16x53.125G
PMD interfaces - 2x400GBASE-DR4 modules
Multi-lane distribution (MLD) to distribute data from a single Media Access Control (MAC) channel across 2x16 PCS lanes
Compliance mode
Customized Alignment Markers
Full duplex operation
Internal and external clock mode
PAM4 modulation scheme
100GPL Features
100GPL interface supported on IEEE802.3ck supports:
