Overview

PMBus Verification IP for your IP, SoC, and system-level design testing.

Incorporating the latest protocol updates, the Cadence® Verification IP (VIP) for PMBus provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. The VIP for PMBus is designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, and helps to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for PMBus runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: PMBus v1.3.1 - Power System Management Protocol Specification Part I – General Requirements, Transport And Electrical Interface and Power System Management Protocol Specification Part II – Command Language.

PMBus diagram

Product Highlights

  • Supports testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Contains predefined checks to verify that the DUT agents, controller and target, adheres to the supported protocol features
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive SystemVerilog coverage

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

MBus Devices
  • Controller, target, or host

Packet Error Checking
  • Performs PEC on transmit and receive data on applicable packets

Address Resolution Protocol
  • Resolve addresses for devices on the bus

Device Timeout
  • Device timeout condition detection

Command Protocol
  • All (Group, Extended, Zone read/write, Host Notify) command protocols with and without a packet error code

Clock Generation and Data Arbitration
  • Clock generation using defined clock timings and data arbitration

Clock Synchronization Between Two Managers
  • Clock synchronization when more than one manager drives the clock

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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