Overview

Best-in-class MIPI® RFFEsm Verification IP for your IP, SoC, and system-level design testing.

Cadence provides a mature and comprehensive Verification IP (VIP) for the MIPI® RF Front-End Control Interface (RFFEsm) protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for RFFE provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for RFFE helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported Specification: MIPI specifications for the RFFE v1.0.0a, v1.10a, v2.0, v2.1, and v3.0.

MIPI RFFE diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Generates constrained-random bus traffic with predefined error injection
  • Callbacks access at multiple queue points for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Dynamic activation to enable setting the VIP as active/passive during run time
  • Provides extensive coverage in SystemVerilog

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Topology
  • Multiple subordinate and multiple main devices topology

Packet Generation
  • Command, Address, Data, and No Response Frame generation
  • Main device supports main write/read and also main context transfer write/read
  • Supports all RFFE commands

Device Address Types
  • Supports MID, GSID, USID, and BSID device addresses

Triggers
  • User-configurable triggers, timed triggers, external triggers and mTrig

Bus Park Cycle
  • Subordinate-initiated bus park, main-initiated bus park, and silent bus park cycle

SSC
  • Generation and detection of Sequence Start Condition (SSC)

Bus Ownership Transfer
  • Main ownership handover for multi-main topology

Modes
  • Normal mode and secondary mode

HSDR
  • Half-Speed Data Response for read access

Programmable USID
  • All three methods to program Unique Subordinate ID

Score Boarding
  • Compares read data with expected data based on none/any/many trigger(s) happening for that address

Error Injection
  • Inject and detect parity errors in any frame (command, address/data), various errors can be injected and detected as well in main ownership transfer command
  • Invalid command frame
  • Manipulate trigger supported register addresses from backdoor

Event Notification
  • Notification for command/address/data frames sent, timed trigger event occurred and reset occurred

Interrupt Capable Subordinate
  • Supports Interrupt Summary and Identification Command Sequence for RFFE v2.0 and RFFE v2.1

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

Master Your Tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles

Learn More

Related Products

System VIP
Protocol IP
Xcelium Logic Simulation
Palladium Emulation