Overview

Gold standard for JEDEC® GDDR6 memory device for your IP, SoC, and system-level design verification.

Sign-off model for dozens of production designs.

This Cadence® Verification IP (VIP) provides support for the JEDEC® Graphics Double Data Rate (GDDR6) SGRAM GDDR6 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for GDDR6 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

GDDR6 diagram

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Dozens of predefined configurations based on specific memory vendors' part numbers, datasheets, or generic JEDEC definitions available on ememory.com
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Ability to optionally skip initializations, trainings or dynamically change configuration parameters
  • Packet tracker creation for easy debugging
  • Extensive functional coverage in SystemVerilog
  • Integrated with the DFI GDDR6 solution for IP level verification
  • Support testbench language interfaces for SystemVerilog, UVM, OVM, and SystemC

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Speed
  • Supports up to 16Gbps with current vendor datasheets

Device Density
  • Supports a wide range of device densities from 8Gb to 32Gb

Device Configuration
  • Supports x16/x8 mode configuration; Supports Pseudo-channel (PC) mode configuration

Bank Architecture
  • 16B and BankGroup supported

Clock
  • CK (DDR), WCK (DDR, QDR), DFS (Clock frequency change)

Supported Commands
  • Write: WOM, WOMA, WDM, WDMA, WSM, WSMA, WRTR
  • Read: RD, RDA, RDTR
  • Precharge: PREab, PREpb
  • Power down: PDE, PDX
  • Self refresh: SRE, SRX
  • Refresh: REFab, REFpb, REFp2b
  • NOP, MRS, Activate, CAT

Initialization
  • Power-up sequence, Stable Power Sequence

Interface Trainings
  • Command address training, WCK2CK training, Read training, Write training

Command Address Bus Inversion
  • The number of CA lines driving a LOW level can be limited to 5 in 2-channel mode or 7 in PC mode for 8Gb, 12Gb and 16Gb densities and limited to 6 in 2-channel mode or 8 in PC mode for 24Gb and 32Gb densities

Data Bus Inversion
  • Data on the bus can be inverted during both read and write to save power. Data Bus Inversion the feature can be set through mode register

Error Detection Code
  • Supports Error Detection Code hold pattern, CRC, and special EDC in other states

Tccd Reads and Writes
  • Supports all combinations of Reads and Writes placed Tccd apart

Self Refresh
  • Supports Hibernate Self Refresh with VDDQ off

Simulation Test Suite

MM has a rich test suite of scenarios for easy MM evaluation and deployment.

Please contact us for further information.

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