Overview

Best-in-class Ethernet Verification IP for your IP, SoC, and system-level design testing.

The Cadence® Verification IP (VIP) for Flexible Ethernet (FlexE) provides a mature, highly capable compliance verification solution for the FlexE protocol stack incorporating bus functional model (BFM) and integrated protocol checkers and coverage. The VIP for FlexE is designed for easy integration in test benches at IP, system-on-chip (SoC), and system levels helping to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet FlexE is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Supported specification: OIF FLEXE-02.1(2019) and IEEE 802.3-2018.

Ethernet FlexE diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e and SystemC
  • Predefined protocol checkers to evaluate the compliance of the DUT model to protocol requirements
  • Generates constrained-random bus traffic with predefined error injection at FlexE Client, FlexE Shim, Phy levels
  • Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation, error injection
  • Waveform Debugger for tracking of transaction fields, FSM states and counters at each layer of FlexE Interface
  • Supports dynamic client reconfigurations without affecting traffic on other clients
  • Packet tracker creation for easy debugging
  • Extensive SystemVerilog coverage model with infrastructure for extension

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

OIF FLEXE-02.1(2019)
  • Channelization/Bonding/Sub-Rating/Hybrid
  • Multiple 50G/100G/200G/400G BaseR PHY
  • FlexE clients of 5G, 10G, 25G, 40G, 50G, 100G, 200G, and 400G speeds
  • Maximum number of FlexE clients supported: 80
  • Maximum number of BaseR PHY supported: 8
  • 5G and 25G granularity
  • Calendar A/B
  • Calendar Resizing
  • Padding and Interleaving
  • Management and Synchronization frames
  • Skew/De-skew

PMA Bus-Width
  • 1, 2, 4, 10, 16, 20, 32, 40, 64, 66, 80, 120, 128, 160

Frame Types
  • Ethernet IEEE 802.3 (type and length defined)
  • Jumbo frame
  • MAGIC frame
  • Version II frame
  • Tagged Frames: Single Tagged (Q-VLAN tag) and Double tagged (S-VLAN tag and Q-VLAN tag)
  • PTP
  • MACSEC

Custom Frame
  • Proprietary header

Clock
  • Single Clock mode - External

Simulation Test Suite

VIP comes along with a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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