Overview
Cadence® PHY IP for PCI Express® (PCIe®) is a silicon-proven IP for a wide range of verticals including consumer (mobile, IoT), enterprise (high-performance computing (HPC)/server/storage), artificial intelligence and machine learning (AI/ML), and automotive, with maximum throughput and minimum latency in normal mode and low-latency exit from standby with ultra-low power.
The PHY product information presented here only covers PCIe 4.0 and below. For PCIe 5.0, 6.0, and beyond, please see PHY for PCIe and CXL.
Key Benefits
High Performance
Single macro supports max 16Gbps with up to 16 lanes for long-reach applications
Mature and Silicon Proven
Compliance proven, customer SoCs in volume production
Low Risk
Fully validated by Cadence’s rigorous IP qualification process and system stress tests
Ease of Use
Fully verified pre-integrated IP delivery, with package and signal integrity support and firmware for rapid bring-up
