Overview
The Cadence® 16G Multi-Protocol PHY is a silicon-proven, high-end SerDes PHY operating at speeds from 1.25Gbps to 16Gbps. It features long-reach equalization capability at low active and standby power with low sub-states exit latency. This PHY IP is compliant with PCI Express® (PCIe®) 4.0, 10G-KR, and SGMII, and provides users with great flexibility to mix and match protocols within the same single PHY macro.
Key Benefits
High Performance
Single macro supports max 16Gbps with up to 16 lanes for long-reach applications
Mature and Silicon-Proven
Compliance-proven customer SoCs in volume production
Low Risk
Fully validated by Cadence’s rigorous IP qualification process and system stress tests
Ease of Use
Fully verified pre-integrated IP delivery, with package and signal integrity support and firmware for rapid bring-up
Features
