Overview
MIPI D-PHY IP
The Cadence® IP for MIPI® D-PHYsm integrates a high-speed transmitter/receiver, low-power transmitter/receiver, and low-power contention detector that provide the full function of D-PHY. Our IP has an integrated PPI interface for ease-of-integration with MIPI CSI-2 and DSI controllers.
The IP for MIPI D-PHY provides lane flexibility with a compact and rectangular IP footprint, meeting usage models of modern SoCs. The pre-integrated CSI-2 and DSI solution ensures the interoperability and makes this PHY easy to integrate, shortening the product's time to market.
MIPI D-PHY Block Diagram
Key Benefits
Available as Pre-Integrated Solution with Controller
Cadence CSI-2 and DSI supported
Scalable, Modular Design
Compact and regular footprint
Supports Advanced FinFET Processes
16nm, 12nm, and 7nm processes supported
Features
