Overview

Industry Leading DSP-Based 112G SerDes Solution

The 112G-ELR SerDes delivers exceptional extended long-reach performance with superior margin, optimized power, and area that is ideal for next-generation cloud networking, artificial intelligence and machine learning (AI/ML), and 5G wireless applications. The SerDes PHY IP supports PAM4 and NRZ signaling and data rates from 1G to 112G and incorporates industry-leading analog-to-digital converter (ADC), clock-data-recovery (CDR), and digital signal process (DSP) technology with maximum likelihood sequence detector (MLSD) that enables support up to 45dB channel.

Key Benefits

Optimal Performance with Production Quality

Production Quality

A large number of customer production tapeouts and SoC proof points.

Robust Performance

ADC/DSP-based receiver architecture with MLSD and reflection cancellation techniques provide superior data recovery for lossy and reflective channels.

Comprehensive Testability

Rich diagnostic toolkit for easy observation and debugging.

Features

Best-in-Class PHY IP Enabling Up To 800G Subsystem Solutions

  • Supports full-duplex 1Gbps to 112Gbps data rates
  • Superior bit error rate (BER) performance across high-loss and reflective channels 
  • Compliant with IEEE 802.3ck and OIF standard electrical specifications
  • Supports flexible SoC floorplan and IP placement and provides package substrate guideline/reference designs
  • Available in multiple advanced-process nodes including 7nm, 6nm, 5nm, 4nm, and 3nm
  • 400G Ethernet PHY + controller subsystem proven in silicon
  • Up to 800G Ethernet subsystem delivery with Cadence High-Speed Ethernet Controllers

Resources

Browse Recommended Resources

Related Products

56G-LR PAM4 SerDes PHY

High Speed Ethernet Controller

224G-LR SerDes PHY