Overview
Cadence® Ethernet SerDes IP solutions address the performance, power, and area requirements of today’s mobile, consumer, and enterprise (infrastructure) markets with extensive standard support for the latest PCI Express® (PCIe®), Ethernet and USB specifications. Available for both low-power mobile applications and high-performance computing applications, the Ethernet SerDes PHY IP is pre-integrated with Cadence controllers and equipped with extensive test features for superior interoperability and the lowest risk path to SoC success.
Key Benefits
Low Power
Low-active and low-leakage optimized design
High Flexibility
Flexible lane configuration with multi-protocol multi-link support
Comprehensive Testability
Extensive testability support for BIST, scan, loopbacks, SoC isolation, and on-chip eye plotter
Features
