16Gbps Multi-Link and Multi-Protocol PHY IP

With the large growth in data and compute demand, enterprise-level data communications, networking, and storage systems are taking center stage in many application areas. High performance and uptime, power efficiency, and small form factor are some of the key requirements for such systems, and these requirements percolate down to components and IP.

The Cadence IP for 16Gbps Multi-Link and Multi-Protocol PHY is a high-performance SerDes operating from 1.25 to 16Gbps, specifically designed for infrastructure and data center applications. It features long-reach equalization capability at very low active and standby power. The SerDes offers very low latency for time-critical applications. 

The 16Gbps Multi-Link and Multi-Protocol PHY provides extensive flexibility to mix and match protocols within the same macro. The PHY IP is designed to simultaneously run PCI Express (PCIe), Ethernet, and SGMII/QSGMII on a per-lane basis. Multiple test features are embedded and easily accessible by the end user. A user-friendly graphical interface called EyeSurf provides convenient access to real-time and non-destructive eye scope and bathtubs for monitoring the bit error rate (BER) and the link performance during live traffic.

The PHY IP is engineered to quickly and easily integrate into any SoC, and to connect seamlessly to a Cadence controller for full flexibility. This minimizes the time and risk of device development. It offers SoC integrators the advanced capabilities, flexibilities, and support for advanced, high-performance designs. The Cadence IP is silicon proven for leading-edge process nodes and has been extensively validated with multiple hardware platforms.

The Cadence IP for 16Gbps Multi-Link and Multi-Protocol PHY provides performance, reliability, and robustness for the most demanding applications. 

The IP is a hard PHY macro with a physical media attachment (PMA) layer and a soft physical coding sublayer (PCS) available for various processes. The PHY supports long-reach (LR) backplane with insertion loss in excess of 30dB. It is specifically optimized to minimize end-to-end latency and power. Low-power modes are also supported (ex. PCIe L1 substrates, etc.) for energy-efficient applications. For robustness, the PHY operates from -40°C to 125°C, features superior ESD protection, and exceeds the stringent reliability requirements of data center applications.

The PCS complies with the latest PCIe PIPE specification and provides support for the dynamic equalization features of different interface protocols. The IP is designed for handling multiple protocols on one single PHY macro (see table below).

The 16Gbps Multi-Link and Multi-Protocol PHY is designed with a multi-link lane-based architecture, providing greater control over floorplanning, placement, packaging, and I/O integration than other hard PHY solutions, while maintaining the reliability and ease of use associated with GDSII macros.

Cadence can deliver various configurations of the IP to meet your design requirements. 

The Cadence IP for 16Gbps Multi-Link and Multi-Protocol PHY is available with various configurations and supports the following protocols:

For more information, visit Design IP.