Overview
MIPI D-PHY IP
The Cadence® IP for MIPI® D-PHYsm integrates a high-speed transmitter/receiver, low-power transmitter/receiver, and low-power contention detector that provide the full function of D-PHY. Our IP has an integrated PPI interface for ease-of-integration with MIPI CSI-2 and DSI controllers.
The IP for MIPI D-PHY provides lane flexibility with a compact and rectangular IP footprint, meeting usage models of modern SoCs. The pre-integrated CSI-2 and DSI solution ensures the interoperability and makes this PHY easy to integrate, shortening the product's time to market.
![MIPI D PHY IP block diagram new web MIPI D PHY IP block diagram new web](/content/dam/cadence-www/global/en_US/images/site-images/silicon-solutions/MIP_D_PHY_block_diagram.png)
MIPI D-PHY Block Diagram
Key Benefits
Features
![Mobile Phone Mobile Phone](/content/dam/cadence-www/global/en_US/images/site-images/silicon-solutions/MIPI/Mobile_Phone_on_side_with_sky_image_B.jpg)