Overview

Best-in-class PIPE PHY Verification IP for your IP, SoC and, system-level design testing.

The Cadence® PIPE PHY Verification IP (VIP) provides a mature, highly capable verification solution for the PHY layer of complex protocols such as PCIe 3/4/5, USB-3.x, USB-4, DisplayPort and SATA at the Intel PIPE (PHY Interface for PCI Express*, SAA, USB-3, DisplayPort, and Converged IO Architectures). The VIP supports simulation platform and enables metric-driven verification of IP and System on Chip (SoC) designs against PIPE PHY protocol specifications. PIPE PHY VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators.

Supported Specifications: Intel PIPE version 4.3, 4.4,1 and 5.2 specifications.

PIPE PHY diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
  • Runs on all major simulators such as Xcelium, VCS, or MTI
  • Extensive PHY-level timing checks
  • Ability to drive protocol-aware and protocol-agnostic traffic for exhaustive testing
  • Built-in scoreboard for analyzing receive path, transmit path and loopback
  • Control over jitter, Spread Spectrum Clock and Bit Error Rate
  • Multi-Lane PHY Support

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Device Type
  • PipeXceiver
  • SerialXceiver
  • PHYDUT Monitor
  • PHY Active VIP

PHY Architecture
  • Original PIPE architecture
  • SerDes Architecture

Pin Interface
  • Legacy Pin Interface
  • Low Pin Count Interface

Protocols Mode
  • USB 3.x
  • PCIe 3/4/5
  • USB4
Data Transmission Rate
  • USB 3.x: 5GT/s, 10GT/s
  • USB4: 10 GT/s. 20 GT/s, 10.3125 GT/s, 20.625 GT/s
  • PCIe: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s,32.0 GT/s

Clock Support
  • External Bit Clock
  • Internal Bit Clock (Recovery from Serial bit stream)

PCLK Modes
  • PCLK as PHY Input
  • PCLK as PHY Output
  • PCLK as both

LFPS
  • Supported

PIPE Data Width
  • 8/10, 16/20, 32/40 and 64/80 bit

Message Bus
  • M2P and P2M Transactions supported
  • All Message bus commands supported
  • Write Uncommitted
  • Write Committed
  • Read
  • Read Completion
  • Write ACK

Integrated Mode with Protocol VIP
  • USB3 , USB4, including Pipe
  • Phy Integrated Mode, is supported

Simulation Test Suite

Extensive testsuite, coverage model, and verification plan with clear linkage to the specification for simple and fast compliance testing.

TripleCheck Test Suite

Master Your Tools

Tutorials, Documentation, and Local Experts

Cadence Online Support

Increase your efficiency in using Cadence Verification IP with online trainings, VIP Portal, application notes, and troubleshooting articles

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