Key Benefits
Chip / Package Co-Design
Create higher performing, lower cost packages
Multi-Chip(let) Design
Robust support for multi-chip(let) heterogeneously integrated designs
Comprehensive Design
Analysis and verification flow for fan-out wafer-level package (FOWLP)
Reference Flows
Support for major foundry and OSAT advanced packaging
Resources
-
Video
Gain PPA Advantages with New Aging-Aware STA Solutions for High-Performance Semiconductor Designs
Watch Now -
Video
CadenceTECHTALK: Meet Advanced IC Package Design Schedule Challenges with In-Design Analysis
Watch Now -
Video
Team Collaboration With Allegro Symphony | Allegro PCB Designer
Watch Now
Training and Support
Need Help?
Training
The Training Learning Maps help you get a comprehensive visual overview of learning opportunities.
Training News - Subscribe
Online Support
The Cadence Online Support (COS) system fields our entire library of accessible materials for self-study and step-by-step instruction.
Request Support
Technical Forums
Find community on the technical forums to discuss and elaborate on your design ideas.
Find Answers in cadence technical forums