Overview
Gold standard for Quad-SPI memory device for your IP, SoC, and system-level design verification.
In production since 2018 for many production designs.
The Cadence® Verification IP (VIP) for Quad SPI provides verification of Q-SPI NOR devices using the SPI protocol. The VIP for Q-SPI is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Supported Specification: Features of all major vendors such as Micron, Macronix, Winbond, Cypress, GigaDevices, and ISSI.
![Q-SPI diagram](https://newstaging.cadence.com/content/dam/cadence-www/global/en_US/images/Products/System-design-and-verification/verification-ip/simulation-vip/diagrams/q-spi-diagram.png)
Product Highlights
Key Features
The following table describes key features from the specifications that are implemented in the VIP:
Feature Name |
Description |
---|---|
Device Density |
|
Operation Mode |
|
RESET |
|
Device Identification |
|
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