Best-in-class MIPI® SoundWire-I3Ssm (SWI3S) Verification IP for your IP, SoC, and system-level design testing.

The Cadence Verification IP (VIP) for SoundWire-I3S (SWI3S) is designed for easy integration in test benches at the IP, system-on-chip (SoC), and system level. The VIP for SWI3S runs on all simulators and supports SystemVerilog along with the widely adopted Universal Verification Methodology (UVM). This enables verification teams to reduce the time spent on environment development and redirect it to cover a larger verification space, accelerate verification closure, and ensure end-product quality. It supports Manager, and a configurable number of peripherals (1-8).

Supported Specifications: MIPI SoundWire-I3S specification version 0.5r02, June 2022.

MIPI SoundWire-I3S Diagram

Product Highlights

  • Support testbench language interfaces for SystemVerilog and UVM
  • Generates constrained-random bus traffic with predefined error injection
  • Callback access at the end of every phase element (starting from PKT_LEN_L), command phase, Sample interval, and Link control sequence on TX and RX path for scoreboarding and data manipulation
  • Packet tracker creation for easy debugging
  • Support of Waveform Debugger

Key Features

The following table describes key features from the specification that are implemented in the VIP for SWI3S:

Feature Name

Sub-Feature Name

Description

PHYs

 
  • Supports LC PHY, FBCSE PHYs (PHY1, PHY2) and DLV PHY

Interfaces

 
  • Supports SWI3S dp/dn or clock/data interface

Devices

 
  • Supports Manager and up to 8 peripherals

Link Control and Reset

Sequences

  • Supports ColdStart and WarmStart sequence, supports peripheral wake requests and Manager acknowledgement

Resets

  • Ability to perform power-on reset and bus reset

Hot-Join

  • Supports configuration-based Hot-Join to wake required PHY without going through ColdStart sequence

LC-PHY

Strength Driving

  • Manager and peripheral supports driving and identifying different drive strengths (weak, strong, supply) modeled as Verilog net strengths

CDS and Command Transport Protocol

Phases

  • Manager and peripheral support GetStatus, Announce, Write, ReadSetup, ReadData, and Commit phases
  • Supports remote read/writes

Codeword Endianness

  • Supports codeword transmission and reception in Little and Big endian mode

Stream Synchronization Point

  • Supports scheduling SSCR/SSPA commands to align commit point with SSP and notifying commit event

Clock-Config

  • Supports dynamic clock config

Transport and Protocol Errors

  • Manager and peripheral support injecting and detecting transport errors (bad 8b-10b symbols, bad robust token, bad opcode, bad CRC etc...) and protocol errors

Payload Transport

 
  • Supports up to 32 Manager or Peripheral data ports and up to 16 channels per data port
  • Each data port can be programmed to control payload transport pattern

Data Port Sequences of Operation

  • Supports all Data Port sequences of operation (start_stream, Insta_start_stream, stop_stream, pause_stream etc.)

FBCSE PHY

 
  • Supports both PHY1/PHY2
  • Supports NRZS encoding of CDS
  • Clock/data setup and hold time can be controlled
  • Supports Clock pause feature
  • Supports bus keeper with weak drive strength and special drive

DLV PHY

Clock and Data Recovery

  • Peripheral can lock to row syncs to generate CDR clock required for DLV PHY
  • Supports bus keeper with weak drive strength and special drive

Registers

 
  • Supports SWI3S-defined registers
  • SWI3S-defined Register space can be accessed through frontdoor (using SWI3S Read/Write commands) or backdoor
 

Phy Control Register

  • Register to control PHY behavior
 

Data Port Registers

  • Registers to control Data Port configurations (ReadyCh, SampleWidth, SampleGrouping, PortDirection, etc.)
 

CDS Transport Registers

  • Registers to configure Control Data Stream transport parameters (CDS_Hstart, CDS_DriveType, CDS_Width, etc.) 

Transport and Protocol Errors

 
  • Manager and peripheral support injecting and detecting transport errors (bad 8b-10b symbols, bad robust token, bad opcode, bad CRC, etc.) and protocol errors
  • Support to modify CDS from callback to inject any type of error in it

Simulation Test Suite

SWI3S VIP has a testsuite of scenarios for easy VIP evaluation and deployment.

Please contact us for further information.

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