Timing Closure

What is Timing Closure?

Timing closure is the process that determines a chip's speed by satisfying the timing constraints. It ensures that all the signals arrive at the correct time for smoother chip operation. However, with chips packing more functionalities and shrinking time-to-market windows, especially at advanced nodes, timing closure is becoming a major problem for design engineers. Complex design rules, low-power circuitry design techniques, and signal integrity issues are just some of the advanced-node challenges impacting design closure.

Larger designs with more functionality require more compute to analyze. Higher frequency targets and lower power envelopes require more Engineering Change Order (ECO) cycles. ECO cycles on large, advanced node designs require many iterations due to unpredictable closure techniques.

As a result, timing closure cycles are often longer, requiring frequent ECO iterations.

Clearly, meeting timing closure requirements is more than just an interview question. It is a challenge for many engineers worldwide. Let's explore these challenges and the available solutions to them.

Challenges in designing for timing closure

Timing closure problems in SoC design have led to the development of entirely new methodologies, calling for more sophisticated tools with different capabilities at every step of the design flow. Updates with the introduction of FinFET were the last significant achievement in timing closure. The time is ripe for another significant innovation in this space.

With the progression of Moore’s Law, new challenges are emerging every day that current tools and methods cannot address efficiently.

Power and thermal analysis drive decisions on the packaging and system-level heat dissipation. In turn, solutions such as multi-die packaging, where the chips, packaging, and boards drive the throughput and power, lead to more pressing demand on proper timing.

Timing is affected by process variability, signal integrity, and IR drop.

Reducing power consumption while meeting the timing goals, called power recovery, is another critical design closure challenge to achieve.

Power recovery (i.e., lowering power consumption while still meeting timing goals) is another important design closure objective.

However, product designs demand more features and power and increased process variation, leading to manufacturing-related issues requiring faster transistors with less power. This complicates on-chip communications infrastructure, increasing the number of logic circuits. One can raise the voltage and lower the clock for set-up violations to achieve timing closure, but it is not just that. Even the same node can be architected for more throughput. These problems need to be addressed earlier in the design cycle for optimum performance.

Factors affecting timing closure

Before discussing the possible solutions to achieving timing closure on schedule, let us take a step back and analyze the physical constraints that govern timing closure.

Changing process geometries

The process geometries of modern Application Specific Standard Products (ASSPs), Application Specific Integrated Circuits (ASICs), or Field Programmable Gate Arrays (FPGAs) now dictate that timing analysis be performed at twenty or more timing corners to guarantee timing closure. At these more minor process geometries, the delays are typically dominated by the delays of the interconnect routing as opposed to the cell delays. This creates a challenge in the placement of the design to avoid long interconnect delays while avoiding routing congestion.

Increased Complexity

Increasing gate count is making designs more complex and achieving timing closure more challenging. For instance, the SoCs are getting bigger and using transistors with less leakage and faster speeds, but the wires used for the on-chip communications and the metal line resistance affect the timing closure. If you decide to increase the distance between the placement of two IPs, you will inevitably have to add repeaters or pipelines to run at the same speed.

Techniques for timing closure

Timing signoff for digital designs in advanced nodes is getting increasingly time-consuming as the last steps in design closure, working against shorter time-to-market windows. Engineers had to develop new signoff technologies to deal with common bottlenecks in timing signoff.

For timing analysis, a hierarchical design method allows teams to collaborate on a single chip, while scope-based timing analysis improves runtime and capacity.

We assert the constraints at block boundaries in the hierarchical method to resolve dependencies. After synchronizing all the data at the block boundary, we perform the analysis. It is an iterative process, with new constraints asserted in each iteration until we meet the convergence criterion.

We also have a novel method of scope-based timing analysis. While both methods have pros and cons, scope-based analysis lets you dynamically abstract only the design portions that require analysis. It works by defining the change space at the same level of granularity as physical/logical block boundaries. The Tempus Timing Signoff Solution analyzes the top-level scope first, then proceeds towards the dynamic abstraction of the design, analyzing the resulting “carved out” design.

The complete design closure depends on power and time signoff, which are interdependent. Switching times affect the current draw. In turn, the power rail voltages affect cell delays. The Voltus IC Power Integrity Solution comes with the Tempus Timing Signoff Solution integration that provides a unified power and timing analysis and closure system. With it, we can achieve convergent iming/IR-drop analysis process, giving us a more accurate static timing analysis, reduced timing pessimism, and a realistic voltage drop across the chip.

Testing for timing closure with static timing analysis

Static Timing Analysis (STA) checks all possible paths for timing violations to validate a design’s timing performance during timing signoff. However, for more complex designs, basic STA might not be enough; distributed static timing analysis (DSTA) is the preferred method of timing analysis of very large designs with more than 400M cells.

Achieve faster timing closure with Cadence

Cadence Tempus Timing Signoff Solution can help you optimize your design for performance and capacity through massively parallelized computation across many CPUs. With full foundry certification down to 3nm and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution delivers accurate results across various design types.