Cadence Modus DFT Software Solution

Overview

Reduce Test Time Up To 3X with the Cadence Modus DFT Software Solution

Concerned about escalating test costs? Reduce your SoC test time by up to 3X with the Cadence Modus DFT Software Solution. This next-generation tool features a new patented 2D Elastic Compression architecture, enabling compression ratios beyond 400X without impacting design size or routing. With a complete suite of industry-standard capabilities for memory BIST, logic BIST, test point insertion, and diagnostics, the solution can help you reduce your production test costs and increase silicon profit margins.

Key Benefits

The Most Productive Design for Test Solution for Achieving High Coverage, Reduced Test Time, and Superior PPA

Complete, Integrated DFT Solution

Natively integrated with the Genus Synthesis Solution or standalone DFT insertion

Compression Optimization

Up to 2.6X reduction in compression logic wirelength—resolves routing congestion issues due to traditional scan compression logic

Innovus Test Points

Unique solution enables maximum coverage and test point sharing with no degradation in PPA

Intelligent Diagnostics

Highest accuracy and resolution diagnostics—faster, smarter insight into yield issues

Features

A Complete DFT Solution Integrated with Physical Design to Achieve High Coverage While Reducing Test Time and Delivering Superior PPA

DFT: UPF Power Aware, Genus Synthesis Solution integration— inserts full scan, boundary scan, compression, low pin count architecture, X-masking, on-chip clock controller, JTAG controller, IEEE 1687 (iJTAG), and IEEE 1500.
ATPG: Static and delay fault test pattern generation, low-power test pattern generation with scan and capture toggle count limits, and distributed test pattern generation with near-linear runtime scalability across multiple machines and CPUs.
Innovus Test Points: Highly differentiated technology that solves the physical implementation problems associated with conventional test points. Innovus Implementation System test points allow maximum sharing, which reduces test time with no implementation PPA degradation.
Diagnostics: Single- and multi-die volume diagnostics, with physical defect location callout and root-cause analysis for logic gates and memories. Simulates multiple defect types concurrently and reorders compressed/uncompressed patterns. Support for advanced fault models, including cell aware.
Programmable Memory BIST: RTL or netlist-level insertion and support for soft and hard repair. Embedded memory bus support integrates seamlessly with a macro interface for at-speed PMBIST across multiple embedded memories in an IP core and support for ARM^® MBIST interface. New programmable test algorithms for FinFET SRAMs and automotive safety applications.
Modus Logic BIST: Production proven in ASIL-D designs. Support for JTAG or direct access. Integrates with 2D Elastic Compression for ease of routability.

Customer Success

Learn how customers use Cadence Modus to reduce test times while automating processes.

Valued customers worldwide attend CadenceLIVE to share the latest design and implementation practices.

Analog Devices

eInfochips

NXP

Texas Instruments

Customer Stories

See What Customers Have to Say

The Modus Test Solution demonstrated a 3.6X reduction in test time on a customer networking chip without impacting design routability or fault coverage. This technology definitely reduces production test.

Sue Bentlage, Director, ASIC Design and Methodology, GLOBALFOUNDRIES

Minimizing the cost of test is crucial in high-volume, price-sensitive markets like embedded processing. The Modus Test Solution is showing a 1.7X reduction in digital test time on one of our largest and most complex embedded processor chips.

Roger Peters, MCU Silicon Development, Texas Instruments

With the Modus Test Solution, we achieved an impressive 2.6X reduction in compression wirelength and a 2X reduction in scan time. The reduction in compression logic wirelength enabled us to address a key challenge for design closure.

Alan Nakamoto, Vice President, Engineering Services, Microsemi Corp.

Test time has a significant impact on semiconductor product costs and production capacity, so reducing test time is important. We have seen the Modus Test Solution achieve a 2X reduction in test time without impacting fault coverage or die size.

Chris Malkin, Baseband IC Manager, Sequans

Resources

Browse Recommended Resources

On-Demand CadenceTECHTALK

What’s New— Enhanced Design Features with Cadence Modus DFT, ATPG, and Diagnostics

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