Cadence Modus DFT Software Solution

Scan compression logic forms a physically aware two-dimensional grid across the chip floorplan. The Modus 2D Compression’s grid structure consumes up to 2.6X less routing resources than traditional “one-dimensional” XOR compression circuits at a 100X compression ratio. Furthermore, the 2D grid structure scales sub-linearly with the compression ratio and at a 400X compression ratio is still no worse for routing resources than the traditional 1D XOR compression at only 100X.

Registers and sequential feedback loops are interwoven with XOR logic in the decompressor circuit. The sequential nature of this circuit enables Modus ATPG to leverage multiple shift cycles to control register values in a single fault-capture cycle. Modus ATPG can also adaptively increase the number of shift cycles in a test pattern to be larger than the scan-chain length to provide yet more controllability to detect tough faults. Modus Elastic Compression is able to achieve compression ratios beyond 400X without any impact on fault coverage or fault diagnostics.

Increasing fault coverage and reducing test time are two key benefits of the Modus TPI flow. With two distinct identification algorithms—deterministic fault analysis to improve coverage by targeting hard-to-test faults caused by high-care bit requirements, and random resistant fault analysis to reduce pattern count by targeting hard-to-test faults caused by resistance to random stimuli—Modus testpoints can effectively close your coverage and pattern count gaps. Tightly integrated into the Genus cockpit, Modus TPI is invoked by the Genus Synthesis Solution during the synthesis process— simplifying the flow for synthesis engineers who may be unfamiliar with TPI. This tight integration, coupled with comprehensive runtime controls such as timing-driven slack-based testpoint selection, uniquely position Modus TPI to meet your testpoint needs.

Analyzing a single silicon failure to root cause through physical failure analysis (PFA) can be very expensive and time consuming. So, to accelerate time to profitability, it’s critical to select failing die that are the most statistically significant in terms of limiting yield ramp, which is where Modus Diagnostics volume analysis capabilities come in. Built on top of the Modus Diagnostics precision diagnosis engine, volume analysis leverages distributed processing and multiple defect diagnosis to enable fast diagnosis of a large number of failing die, and then loads these failures into a high-speed SQL database for further analysis. Once the database has been created, Modus Diagnostics volume analysis analyzes the failures for trends, and generates Pareto charts and wafer maps to identify the critical-yield-limiting failures. Silicon defects representing these limiting-defect classes can then be sent to PFA with confidence that the results of the analysis will improve yield fast.

Effectively managing power consumption during silicon test is very critical. Testing at too low a power level means power-sensitive defects could be missed, while testing at too high a power level means the power grid or tester could be over-driven, resulting in false fails and yield loss. Modus ATPG is a comprehensive low-power test solution starting with CPF and IEEE 1801 power-intent-driven DFT insertion in the Genus cockpit, coupled with Q-pin and clock gating to control test mode power. Modus ATPG low-power capabilities include both scan and capture toggle-rate controls, permitting the generation of a pattern set that strikes the right balance and most closely mimics functional power consumption at the tester. For even lower ATPG switching rates, the Cadence Modus DFT Software Solution implements a hardware-based approach inside of the Genus solution to drive power down without impacting coverage.

Cadence is a long-standing leader in mixed-signal design, and is committed to the total interoperability of all of our tools through the OpenAccess database. The Cadence DFT Software Solution natively integrates all DFT insertion with the Genus Synthesis Solution, which natively reads and writes OpenAccess. Since many mixed-signal designs are small, high-volume, low-margin catalog parts, the Cadence DFT Software Solution offers a low-pin-count test to address package and pin limits and enable scalable multi-site testing. To prevent X-sources from adversely affecting digital testing, automated IEEE 1500 wrapper insertion efficiently performs analog isolation. Modus Diagnostics is integrated with the Virtuoso Layout Suite via the OpenAccess database, enabling automated bridging fault-model generation critical to improving yield on highvolume devices, and logical-to-physical cross-probing during diagnosis to enable fast defect location visualization.

Automotive designs are growing aggressively in terms of size and complexity, and the ISO 26262 safety standard is demanding higher manufacturing test coverage (99.9%) and zero DPM—posing big challenges for automotive device designers. Modus Logic BIST combined with TPI is the perfect combination for meeting ISO 26262 demands. LBIST insertion and checking occurs natively in the Genus cockpit, simplifying the incorporation of LBIST including X-state blocking, and Modus TPI dramatically increases the LBIST coverage achieved during the short functional LBIST test cycles dictated by the safety standard. In addition, the Cadence Modus DFT Software Solution’s flexible fault modelling enables a variety of defect modeling methodologies to minimize DPM, including cell-internal, gate-exhaustive, cell-aware, and bridging defect modelling. Memory BIST (MBIST), IEEE 1500 support, and a broad compression portfolio round out the complete Cadence Modus DFT Software Solution for the automotive segment.

The Cadence Modus DFT Software Solution is a part of the tools and flows that have achieved TÜV SÜD’s first comprehensive “Fit for Purpose - TCL1” certification in support of the automotive ISO 26262 standard. Cadence flows are fit for use with ASIL A through ASIL D automotive design projects. Automotive chip designers can verify certification through the TÜV SÜD certification database.