Joules RTL Power Solution

OVERVIEW

Deliver 20X Faster Time-Based RTL Power Analysis

Getting an accurate measure of RTL power consumption during design exploration has long been a major challenge for SoC design teams. System-level verification tools have the capacity to exercise real use cases, but they are disconnected from the implementation tools that translate RTL to gates and wires and from signoff tools that validate the final design.

Cadence Joules RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes and capacity while still providing high-quality estimates of gates and wires.

KEY BENEFITS

Delivers Unmatched Power Reductions in RTL and During Implementation

Power Accuracy

RTL power estimates within 15% of signoff, including glitch power from RTL stimulus

Productivity

Up to 20X faster time-based power analysis, with unique ideal power-guided RTL power reduction methodology

Verification Integration

Direct integration with Palladium and Xcelium platforms for power analysis of workloads, identifying critical windows of interest

Implementation Integration

Native integration inside Innovus, Genus, and Stratus HLS technologies for automatic power optimization

FEATURES

Industry’s Most Accurate and Integrated RTL Power Solution

Single power engine – The Joules power engine is used at all stages of the design flow, from early RTL power estimates, high-level synthesis, RTL synthesis, P&R, to gate-level analysis. No need to switch tools or deal with correlation issues.
Accurate RTL power estimates – Uses implementation engines from Innovus Implementation System and Genus Synthesis Solution to deliver trusted power estimates to RTL designers, including clock tree, high fanout net, and DFT logic impacts.
Ideal power – A unique methodology guides the RTL designer for removing wasted power and activity in their design.
Integrated automated power reduction – Integrated into Innovus, Genus, and Stratus HLS technologies for power analysis and automated advanced power reduction.
Power replay – Gate-level delay-based stimulus accuracy with RTL/zero-delay input. Achieve 100% cycle-accurate, bit-level power activity from RTL word-level stimulus. Standalone and integrated with Genus and Innovus implementation.
Glitch power – Accurately analyze and reduce glitch power on designs using RTL stimulus. Automated reduction during implementation.
Energy analysis – Robust reporting and analysis of energy, not just power.

RESOURCES

Browse Recommended Resources

video

Fast Accurate RTL Power Analysis with Joules RTL Power Solution

Software Engineering Group Director Kamlesh Madheshiya discusses fast, accurate RTL power analysis with the Joules™ RTL Power Solution. Discover how Joules bridges the gap between verification, implementation and signoff, delivering time-based RTL power analysis with system-level runtimes and capacity while still providing high-quality estimates of gates and wires. To learn more visit cadence.com/joules