Cadence® Joules™ RTL Design Studio allows RTL designers to rapidly get early and accurate insight into the physical design effects of power, performance, area, and congestion (PPAC). Front-end designers can locate problems in the design layout, trace them to the source code, and automatically give actionable guidance to improve RTL for better PPAC. Simultaneously, implementation engineers benefit from this early debugging because they can now allocate resources to fix issues that cannot be fixed at the RTL level.

Overview

Cadence® Joules™ RTL Design Studio allows RTL designers to rapidly get early and accurate insight into the physical design effects of power, performance, area, and congestion (PPAC). Front-end designers can locate problems in the design layout, trace them to the source code, and automatically give actionable guidance to improve RTL for better PPAC. Simultaneously, implementation engineers benefit from this early debugging because they can now allocate resources to fix issues that cannot be fixed at the RTL level.

In the past, RTL designers were siloed from implementation engineers, creating a disconnect between the front end and implementation. This disconnect caused extra back-and-forth iterations between the two teams, prolonging the design cycle and significantly delaying time-to-market. Major timing and congestion issues should be resolved before handoff to achieve effective physical implementation. It is possible to solve 20%-40% of the physical implementation challenges in the RTL coding and architecture1 if accurate estimates and intelligent debug are available early enough.

Joules RTL Design Studio assures front-end designers that the source code handoff will be fully optimized and able to achieve PPAC goals. The solution’s PPAC estimates are driven by the core engines from Cadence’s industry-leading Innovus™ Implementation System, Genus™ Synthesis Solution, and Joules RTL Power Solution, meaning that users can trust the accuracy of their design decisions. Its unique intelligent debugging assistant system sets Joules RTL Design Studio apart. This expert system triages possible causes of violations, and the additional insights empower designers to understand how to address issues in their RTL, leading to smarter and more efficient products.

Joules RTL Design Studio has tight integrations with the generative-AI solution, Cadence Cerebrus™ Intelligent Chip Explorer, to explore design space scenarios, such as floorplan optimization and frequency versus voltage tradeoffs. In addition, the Cadence Joint Enterprise Data and AI Platform integration allows trend and insight analysis across different versions of the RTL or across previous project generations.

Key Features and Benefits

One-of-a-kind intelligent RTL debugging assistant system
  • Provides early power, performance, area, and congestion (PPAC) metrics as well as actionable debugging information throughout the design cycle—logical, physical, and production implementation
  • Engineers can perform “what-if” scenarios and potential resolutions to minimize iterations and improve design outcomes.
  • Up to 25% quality of results (QOR) improvement in RTL
Supports both RTL and implementation database input
  • Allows front-end designers to help debug and solve implementation issues
Based on proven engines
  • Joules RTL Design Studio shares the same trusted engines as the Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, enabling trusted prototype accuracy
Shortened TAT and increased productivity
  • 5X productivity improvement with faster physical estimates and reduced runtime compared to full production physical synthesis flow
  • Intelligent feedback translates into faster and fewer iterations
Unified cockpit
  • Provides RTL designers with an efficient, user-friendly experience, offering physical design feedback, localization and categorization of violations, bottleneck analysis, and cross-probing between RTL, schematic, and layout
  • Access all analysis and design exploration features from a single GUI for optimal quality of results (QoR)
Advanced RTL design features
  • RTL Restructuring – modify logical hierarchy; group, ungroup, move, add, or remove instances and rewrite RTL to achieve better PPAC
  • Tracking PPAC – compare QoR between runs or between stages of the same runs
  • RTL Diff – highlights differences in RTL at multiple abstraction levels, from simple RTL changes to complex logic changes
Lint checker integration
  • Allows engineers to run lint checkers (design, activity, UPF, physical, and constraint checks) incrementally to rule out data and setup issues up-front, reducing errors and time to completion
Interactive congestion hotspot layout viewer
Fig 1: Interactive congestion hotspot layout viewer with HDL cross-probing
Timing debug HDL viewer
Fig. 2: Timing debug with HDL cross-probing

OS Platform Support

Joules RTL Design Studio supports:

  • RHEL supported tested 7.4, 7.4+, 8, 9
  • SLES 12,15
  • CentOS 7.4+

Cadence Services and Support

  • Cadence application engineers can answer your technical questions by telephone, email, or the internet—they can also provide technical assistance and custom training
  • Cadence certified instructors teach more than 70 courses and bring their real-world experience into the classroom
  • More than 25 Internet Learning Series (ILS) online courses allow you the flexibility of training at your computer
  • Cadence Online Support gives you 24x7 online access to a knowledgebase of the latest solutions, technical documentation, software downloads, and more
  • For more information, please visit support and training.

References

  1. Vanderlip, Jeff. "Physical RTL optimization solves problems early." EETimes DesignLines. November 15, 2002.