Jasper RTL 应用
智能化形式验证Apps通过结合机器学习,来提高验证效率
Key Benefits
- 与其他验证方法相比,可以用更少的时间,在设计流程中更早的发现更多漏洞
- 智能验证技术依托机器学习技术,将开箱即用型验证速度提高 2 倍,将回归测试速度提高 5 倍
- 先进的设计可扩展性,将可执行的设计规模上限提高 2 倍,将内存占用缩减 50%
- 采用直观的分析 GUI,实现具有签核级精度的形式验证覆盖率
- 轻松进行调试和假设分析
Cadence® Jasper™ RTL 应用搭载机器学习技术,借助核心形式验证技术以增强性能。
智能验证技术
Jasper RTL 应用代表了目前最先进的验证求解器算法和编排性能提升。该产品结合了智能验证技术,以提高验证吞吐量,并使用机器学习来进行选择和求解器参数化,确保快速实现验证一次成功。此外,机器学习还在本地或云中发挥作用,优化回归测试的流程。借助智能验证技术,将开箱即用型验证速度提高 2 倍,将回归测试速度提高 5 倍。
先进的设计可扩展性
如今,系统级芯片设计的规模和复杂性与日俱增,设计的编译流程决定了启动形式验证分析所需的计算资源以及设计的最大规模限制。Jasper RTL 应用提供超过 2 倍的设计编译能力,在编译过程中平均减少 50% 的内存使用。此外,工程师可以通过先进的并行编译技术有效地扩展对设计规模的支持能力,以最佳效率利用可用的计算资源,并在云中运行验证流程。
形式验证签核增强功能
形式验证覆盖率技术使工程师在 Jasper RTL 应用中就可以进行 IP 签核。这些形式签核技术包括:提升验证核心和检查器覆盖率的准确度,利用技巧从深度查错中得出有意义的覆盖率,以及形式验证覆盖率分析视图。利用强大的 Jasper Visualize™ Interactive Debug Environment(集成了 QuietTrace™ 调试功能),轻松进行调试和假设分析。这些功能强强联手,可提供签核级别的覆盖率指标,实现多引擎芯片级验证收敛。
申请获取白皮书,了解 post-silicon 调试、属性综合、低功耗、寄存器传输级 (RTL) 设计签核、Superlint 和缓存一致性协议方面的形式验证技术。
了解客户如何评价 Jasper RTL 应用
单击进入下一部分,获取文章和演示。
文章
- Cavium Adopts JasperGold Architectural Modeling 作者:Paul McLellan,SemiWiki
- How I Unwittingly Started BRCM's Formal Verification Users Group 作者:Normando Montecillo,Broadcom
客户演示
- Evolution of Formal Usage in Arm® Austin CPU Group (JUG 2014) 作者:Ross Weber,ARM
- ccelerating SoC Verification By Using Formal Apps in the DV Flow (CDNLive India 2015) 作者:Siva Evani,Analog Devices
- Code Coverage Closure Using Formal Technique (CDNLive India 2014) 作者:Kranthi Kumar、Sravani Tripura、Neelamekakannan,IBM;以及 Nitin Neralkar
- Formal Verification of Packet Processor (JUG 2015) 作者:Dinker Patel,Broadcom
- Code Coverage Formal Unreachability Analysis (CDNLive EMEA 2015) 作者:Ricardo Dantas,Dialog Semiconductor
- Bug Hunting in Deep State-Space(JUG 2015 最佳论文奖得主) 作者:Jim Kasak,Hewlett-Packard Company
- Formal Sign-off with Formal Coverage (JUG 2015)作者: Ashutosh Prasad 和 Vigyan Singhal,OSKI Technology;以及 Vikram Khosa,ARM
- Getting Formal with vManage (JUG 2015) 作者:Stuart Hoad,PMC Sierra
- Why All Designers Should Do Unit-Level Verification (and Hopefully Using a Formal Tool) (When Effective) (CDNLive Israel 2015) 作者:Ofer Sobel,Qualcomm Technologies
- NoC Functional and Deadlock Verification Using Formal (CDNLive India 2015) 作者: Deepti Kansal、Supriya Bhattacharjee、Nirmal Arumugam、Sr. 和 Maruthi Srinivas,Qualcomm India Private Limited
- IPK Use, Reuse, and New Development (JUG 2015) 作者:Lun Li,Samsung
- Solve Functional Verification Challenges Using Smart Formal Verification Approaches (CDNLive India 2015) 作者:Harish M 和 Ashwini Padoor,Texas Instruments
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Jasper RTL 应用
- Jasper FPV App
- Jasper Sequential Equivalence Checking App
- Jasper Design Coverage Verification App
- Jasper Coverage Unreachability App
- Jasper X-Propagation Verification App
- Jasper Control and Status Register App
- Jasper Connectivity Verification App
- Jasper Superlint App
- Jasper Behavioral Property Synthesis App
- Jasper Low-Power Verification App
- Jasper Security Path Verification App
- Jasper Clock Domain Crossing App
- [REDIRECT] Assertion-Based Verification IP
- Jasper FSV App
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Cadence 宣布收购 Rambus PHY IP 资产 07/20/2023
As long-time customers of Incisive formal and simulation solutions, we are impressed with the next-generation JasperGold platform. As well as improved debug and ease-of-use, we’ve achieved a significant increase in performance compared to Incisive Enterprise Verifier, as measured by proof convergence in a given time.
Mark Dunn, Executive Vice President, Imagination Technologies
"With the ability to find bugs weeks earlier in the design process, we’ve reduced late-stage RTL changes, which enables the team to save additional time when we get to the functional verification stage.”
Hobson Bullman Vice President and General Manager, Technology Services Group, ARM
“We’ve identified functional and structural CDC issues earlier in the RTL signoff phase using the JasperGold CDC App. Eliminating these bugs earlier in the process has increased the quality of our designs and saved us between two and four weeks on the design and verification time for each of our IP.”
David Vincenzoni Design Manager at STMicroelectronics
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