Versatile, Ultra-Low-Power DSP for Audio, Voice, Vision, AI

HiFi 1s provides three benefits. First, it supports auto-vectorization by compiler to eliminate the need for hand-optimization, and thereby opening to every embedded programmer. Second, it enhances the always-on AI capability to allow higher-performance ML algorithms to run on an ultra-low power DSP. Third, it adds imaging ISA to support lightweight always-on vision processing.

Auto-vectorization support unburdens the programmer from expert-level hand-optimization, opening the HiFi 1s DSP to a vast pool of non-DSP programmers, lowering development costs, and accelerating TTM. The expanded AI and imaging ISA allow lightweight vision and machine learning applications to run at ultra-low power levels. Double-precision ISA helps modern audio programs run efficiently.

cubes image
HiFi diagram

Auto-Vectorization, Expanded AI/ML, Versatility with Imaging ISA

Auto-Vectorization

Enables the compiler to automatically vectorize data arrays to utilize the SIMD structure of HiFi 1s. Eliminates the need for hand-optimization

Expanded AI and Base platform Performance

Dedicated MACs and ISA enhancing ML/AI and upgraded base platform to LX8, allowing richer applications to run at ultra-low power levels

Lightweight Imaging and Vision

Imaging targeted ISA and MACs for always-on lightweight vision applications to run standalone or in conjunction with a Vision DSP

Double-Precision Floating-Point

Greatly accelerates double-precision math functions found in audio and voice code, obviating the need to tradeoff precision with range

Small Battery-Efficient DSP for Always-on Audio, Vision, and AI/ML

  • All the features of HiFi 1 DSP
  • All acceleration with 8x8 and 8x16 MACs dedicated ISA
  • Imaging ISA and 32 8-bit (and 8x16) MACs for lightweight vision applications
  • Double-precision acceleration hardware for Audio and Vision math functions
  • Auto-vectorization support for porting efficiency and fast TTM

Feature

HiFi 1s

Load Units

1

VLIW Slots

2

Scalar operations

2 slots

Accumulator Width

64-bit

Auto-vectorization

Yes

Fixed Pt MACs per

cycle

32x32

1

32x16

2

16x16

4

8x16

8

8x8

8

SP/HP FPU (integrated, optional)

2x4-way/2x8-way

DP FPU (integrated, optional)

Scalar

Imaging/Vision ISA

Yes

Expanded Instructions for NN

Yes

Arithmetic decoding

Yes

AVS (Huffman and bitstream operation)

Yes

Coremark

5.25

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Cadence, through its Tensilica processor IP, brings together best-in-class products and services from industry leaders to help you accelerate the development of your SoC designs while meeting your demanding power and performance requirements. Browse the list of Tensilica processor IP service partners below.

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