Ultra-low energy DSP for always-on applications

Overview

Versatile DSP Combining Traditional Signal Processing, Codecs, and AI Functions

The Cadence^® Tensilica^® HiFi 1 DSP is the smallest and lowest power member of the HiFi DSP family, developed for battery-constrained applications, such as mobile, hearables, wearables, laptop, automotive, and IoT. Its small area reduces SoC cost. It accelerates artificial intelligence (AI) functions with neural network (NN)-specific ISA and architectural features. It is ideally suited for always-on use cases with sensor fusion or voice/face trigger, along with running codecs and DSP/AI algorithms for pre-processing and post-processing.

Key Benefits

Cycle and Energy Optimized for Target Applications

Sensor Fusion

The HiFi 1 DSP supports sensor fusion concurrent with control and signal processing. It embraces modern algorithms with support for base (light to medium) AI acceleration. Several software partners bring the best sensor fusion software to the HiFi 1 DSP.

Smallest DSP

The Tensilica HiFi 1 DSP for Audio is the smallest of the HiFi DSP family, reducing SoC cost as well as standby/leakage power.

Lowest Energy DSP

The Tensilica HiFi 1 DSP has the lowest energy consumption of the HiFi DSP family.

Always-On, Always-Listening

The Tensilica HiFi 1 DSP is well-suited to voice trigger, face trigger, and sensor fusion functions that need to be always on, while preserving battery.

Features

Smallest HiFi DSP, Battery Friendly and Cycle Efficient

Always-On Architecture

Cycle and energy efficient for Bluetooth and Bluetooth Low Energy (BLE) codecs for speech and music
Efficient neural network acceleration ISA and architecture support
Efficient fixed-point DSP operations
Optional vector floating point unit for easy "MATLAB to Optimized DSP" porting
Synthesizable over wide frequency range enabling dynamic voltage-frequency scaling (DVFS) for optimal energy/performance operations

Key Features


VLIW Slots		2
Accumulator Width		64-bit
Fixed-Point MACs per Cycle	32x32	1
	32x16	2
	16x16/8x8	4
FPU (integrated, optional)		Single-precision, two-way vector FPU with low latency
Instructions for NN		Yes
Arithmetic Encoding/Decoding		Yes
AVS (Huffman and bitstream operation)		Yes
Conditionals		Energy-efficient vector Boolean register
Coremark		4.99
User-Defined Instructions		Yes

Partners

Cadence, through its Tensilica processor IP, brings together best-in-class products and services from industry leaders to help you accelerate the development of your SoC designs while meeting your demanding power and performance requirements. Browse the list of Tensilica processor IP service partners below.

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Technologies

オートモーティブ向け機能安全

テンシリカのプロセッサは、既製のプロセッサ/DSP IPであれ、特定のアプリケーションに特化したカスタム・ドメイン・プロセッサであれ、機能安全アプリケーションを可能にすることをお約束します。

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テンシリカ・プロセッサ・テクノロジー

差別化、市場投入までの時間短縮、柔軟性の向上、最高のパフォーマンス、電力、面積を得るために

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TIE（Tensilica Instruction Extension）

パフォーマンス、エネルギー効率、差別化を最適化するDSP/プロセッサのカスタマイズ

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開発ツールチェーン

お客様のアプリケーションに完全にマッチし、構築しながら最適なプロセッサが得られることを保証します。

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Training & Support

Need Help

Cadence is committed to keeping design teams highly productive with a range of support offerings and processes designed to keep users focused on reducing time to market and achieving silicon success.