UVM Verification

What is UVM Verification?

Universal Verification Methodology (UVM) verification is a set of standards, tools, and APIs for creating a universal way of verifying designs. This API/ methodology is meant for building functional testbenches for SoCs. UVM being constructed in SystemVerilog is supported by simulators from all vendors, enabling you to be more productive during the digital design process. End users can consider it a toolbox with tools and instructions for important verification tasks.

UVM helps companies develop modular, reusable, and scalable test benches that can be deployed across multiple projects.

The Accellera Systems Initiative worked with leaders in SoC and EDA to develop UVM. It was subsequently submitted to IEEE for standardization as IEEE 1800.2. Industry was quick to adopt the standard due to the interoperability and reusability of IP and the availability of a UVM-trained workforce.

Before UVM, verification at various companies had similarities but needed more universal acceptance and reusability. Fragmentation is sometimes good in specific industries, but it was a significant downside for verification in electronic design. This is primarily why UVM has completely transformed the process.

Why is UVM verification important?

The main benefit of UVM verification has to do with its standardization station across the industry. The major EDA vendors and IP providers support UVM, resulting in broad support across different tools and verification IPs, (VIPs). Interoperability and reuse are the name of the game. Engineers can easily integrate a VIP into a verification system due to the standardized interface. While functional behavior may differ, the plug-and-play nature remains consistent as long as the standard is adhered to. As usage of UVM has grown, companies can be confident that experienced engineers will have extensive knowledge of general UVM methodology.

UVM is also very stable and proven in thousands (likely 10s of 1000s or more) of designs. There have been a few iterations (V.1, V1.1, and V2.0 with each stable over many years) each building upon the past to add functionality and refinements. It’s a stable standard that has a long history in industry.

Why is UVM so important? SystemVerilog provides the base language features to build testbenches but doesn’t lay out a methodology/process for verification. It’s the nails, screws, hammer, and screwdriver, but has no instructions. UVM takes proven methodologies from both the hardware and software world to build a structure of programming/methodology to create a framework for verifying IPs and SoCs.

Part of the standard provides a process for connectivity and flow of a testbench to ensure compatibility across various teams. It focuses on reusability and extendibility to ensure you don't reinvent the wheel every time you start a project.

For example, imagine you wanted to buy a preexisting IP from a vendor. Without UVM there is no standard to define the interoperability of the IP block or the features it shall include (scoreboard, agent, monitor, sequencer, etc). Much time will be spent integrating the block into your environment and there is no guarantee the needed hooks are provided. UVM ensures a standard across the whole industry, which helps you minimize the time spent on integrating IP that has already gone through that process. Everyone is pulling in the same direction, so the improvements on the UVM from one vendor eventually filter down to everyone. There is a large pool of engineers to hire from with experience in UVM. You can still do things your own way, but UVM makes it easy for you to have a general methodology and capabilities that everyone else in the industry also supports.

Specifically:

UVM delivers an open, unified class library and methodology for interoperable VIP.
UVM allows for block-level up to system-level verification.
Ensures interoperability among multiple verification components.
You can buy preexisting code like IP and intellectual property, which is already UVM compatible. This makes it much easier to integrate into your environment.
You can hire engineers experienced in UVM and they are immediately able to contribute.
UVM is based on a base-class library proven in thousands of projects and provides built-in automation and testbench capabilities.
UVM supports module-to-system and project-to-project reuse and incorporates the collective verification knowledge of Accellera members.
UVM runs on any simulator supporting the IEEE 1800 standard and enables multi-language plug-and-play VIP.

Ultimately, UVM gives much flexibility and the ability to do things your way while pointing everyone in the same direction, making processes compatible.

UVM verification with Cadence

Since UVM is mostly a methodology and framework, it is integrated into Cadence's EDA tools. Cadence is also a part of the standards body, Accellera, responsible for designing and shaping the future of UVM. It also means you can be confident that our tools comply with the latest standard version.

Furthermore, our products seamlessly support UVM at their core. Our membership in the standards body also means extensive support and compatibility with the standard. We allow you to do the entire verification process seamlessly and smoothly using our industry-standard tools. While our support for UVM is quite extensive, it is crucial to highlight some of the tools where UVM will matter the most for the user.

Cadence verification is comprised of core engines and applications that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.

Cadence Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC^®, e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning-based test compression, and functional safety, that enable design teams to achieve verification closure early for IP and SoC designs.

Cadence Verisium Manager automates end-to-end management of complex verification projects from planning to closure. Verisium Manager tightly integrates with the Cadence Verisium Artificial Intelligence (AI)-Driven Verification Platform, leveraging big data and AI to reduce silicon bugs and accelerate time to market. It is built on the Cadence.AI Generative AI Platform, providing the best multi-engine, multi-run, multi-user, and multi-site verification management capabilities.

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