Cadence Tensilica Offerings

Tensilica Processor Technology

Today’s smart connected world with pervasive intelligence at edge nodes for smart sensory computing is driving the requirements for higher bandwidths and increased compute complexity and throughput. Designers using traditional approaches like general-purpose CPUs and DSPs, FPGAs, and dedicated fixed RTL are experiencing several roadblocks such as lower performance and data throughput due to the use of bus interfaces, high power consumption, lack of programming flexibility for future-proofing, longer time to market, and so on. Cadence^® Tensilica^® processor technology offers to overcome these roadblocks and bring innovation to the forefront.

• Data throughput: Allows designers to bypass the main bus entirely, directly flowing data into and out of the execution units of the processor using a FIFO-like process, just like a block of RTL
• Fit into hardware design flow: Only processor core company to provide glueless pin-level co-simulation of the instruction set simulator (ISS) with Verilog simulators, allowing designers to simulate the processor in the context of the entire chip
• Processing speed: Patented automated tools help designers customize their processor for the application, such as video, audio, or communications, allowing them to use Tensilica DSPs to get 10X to 100X the processing speed of traditional processors and DSP cores
• Customization challenges: Most designers are not processor experts and are hesitant to customize a processor architecture for their needs—with our automated processor generator, designers can quickly and safely get the customized processor for their exact configuration
• Time to market: Using processors simplifies ASIC design, accelerates system modeling, and speeds hardware finalization, which in turn gets the product to market faster

Tensilica Instruction Extension (TIE)

The Cadence^® Tensilica^® Instruction Extension (TIE) language is a processor description language that provides a powerful way to optimize Tensilica Xtensa^® processors and extend the functionality of the processors by defining custom execution units, register files, I/O interfaces, load/store instructions, and multi-issue instructions without having to worry about pipelining, control/bypass logic, and interfacing to other processor modules as the instruction extensions are integrated directly into the Xtensa processor pipeline.

With a few lines of TIE, the designer can make a dramatic difference in the Xtensa processor’s performance and flexibility for targeted tasks:

• Create new instructions to increase processor performance and efficiency
  • Reduce bandwidth of standard size transfers and define the exact data width needed for your application
  • Fusion: Merge serial operations into a single instruction that can be issued back-to-back to achieve single-cycle throughput
• Exploit data-level parallelism
  • Create SIMD registers and operations, and perform the same operation across multiple elements of a vector word
• Exploit instruction-level parallelism
  • Create multi-operation instructions using the Xtensa Flexible Length Instruction eXtensions (FLIX)—a multi-issue VLIW with variable slot widths
• Increase data bandwidth—connect to RTL blocks, memories, or other processors via custom processor interfaces without going through the system bus, reducing I/O bottlenecks and improving data throughput
  • Ports (general-purpose I/O, or GPIO) for point-to-point direct connections without flow control
  • Queue (FIFO) interfaces for point-to-point data transfers that require flow control
  • Memory lookup interfaces to connect to arbitrary-width memories or RTL blocks for low-latency data transfers