Design and Verification Language and Methodologies Domain Certification Training
版本 | 区域 | |
---|---|---|
1.0 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 17 Days (136 hours)
Become Cadence Certified
Course Description
Become Cadence-certified in the Design and Verification Language and Methodology domain by taking a curated series of our online courses and passing the badge exams for each course.
- First, we provide detailed learning of Verilog as a design and verification language with labs.
- Then, we switch to the industry's latest SystemVerilog design and verification language constructs with labs.
- We then jump to the most adopted verification methodology in the industry, the universal verification methodology or the UVM course with excellent labs.
- We then shift gears and focus on learning SystemVerilog assertions, which forms a pre-requisite for the formal verification domain.
- The final course is called Formal Fundamentals, which in detail explains concepts of formal verification and the Jasper™ tool apps.
Learning Objectives
After completing the certification program, you will learn about:
- Verilog language and its application in design and verification streams
- SystemVerilog language and its application in design and verification streams
- UVM as a verification methodology
- How to write SystemVerilog assertions
- Fundamentals of formal verification using the Jasper tool
After completing the certification program, you will be able to:
- Use fundamental Verilog constructs to create a simple design
- Ensure that Verilog designs meet the requirements for synthesis
- Develop Verilog test environments of significant capability and complexity
- Understand and use the SystemVerilog RTL design and synthesis features, including new data types, literals, procedural blocks, statements, and operators, relaxation of Verilog language rules, fixes for synthesis issues, enhancements to tasks and functions, new hierarchy and connectivity features, and interfaces
- Use the SystemVerilog RTL design and synthesis features, including new data types, literals, procedural blocks, statements, and operators, relaxation of Verilog language rules, fixes for synthesis issues, enhancements to tasks and functions, new hierarchy and connectivity features, and interfaces
- Understand the features and capabilities of the UVM class library for SystemVerilog
- Create, configure and customize reusable, scalable, and robust UVM Verification Components (UVCs)
- Combine multiple UVCs into a complete verification environment
- Integrate scoreboards, multichannel sequencers, and register models
- State the motivation and methodology of using Assertion Based Verification (ABV)
- Define sequential and boolean properties and all of the different ways of aborting them
- List all the different ways of defining a property clock, including multi-clocked properties
- Demonstrate, with examples, good and bad SVA coding styles and show techniques for the most efficient creation of complex assertions
- Describe common behaviors that SVA cannot describe and how to overcome these issues
- Define reusable, functionally correct SVA properties that are efficient for formal tools
- Set up, run, and analyze results from Formal Analysis, having identified designs upon which formal is likely to be successful
- Understand formal complexity issues and how to overcome them
- Create a complete formal environment from scratch given only a DUT functional specification
- Set up and run Superlint and X-Propagation apps
Software Used in This Course
This certification program contains several courses, each with its own software requirements. Refer to each of the course links provided in the course description and course contents for the specifics.
Software Release(s)
Each course URL contains the software release information for that course.
Modules in this Course
Audience
- Electronics or Computer Engineering students
- CAD Engineers
- Place and Route Engineers
- Design Engineers
- ASIC Designers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- Programming
- Electronics or Computer Engineering
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