Post-LVS Chip-Level EM Crosstalk Analysis and Signoff

Dr. Claudia Roesch, Cadence product engineering director, explains a seamless layout-driven electromagnetic (EM) signoff flow made possible with the Cadence EMX Planar 3D EM Solver and the Quantus Extraction Solution operating within the Cadence Virtuoso RF Solution design environment. The integration of multiple EM solvers into the environment automates the hours of manual work required to run critical passive components and interconnects in the Virtuoso Layout Suite, enabling engineers to run multiple design experiments in a fraction of the time. Automatic layout pre-processing reduces simulation run time to perform post-LVS chip-level EM crosstalk analysis. The EM assistant helps generate and manage all EM models created by the RF engineer, making sure the correct set of models is used in circuit simulation and the layout stays updated without any need for the user to manage multiple layout views when running experiments of various layout structures.