Past Events

On-Demand CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges

The last webinar series, "Adopting a Faster, More Efficient Path to Multi-Chiplet Design," will address the growing system analysis challenges 3D-IC designers face related to signal, power, and thermal integrity and will demonstrate how facing these concerns through simulation during system planning and signoff accelerates the 3D-IC design cycle.

CadenceLIVE China 2022

CadenceLIVE China​ 2022 brings together Cadence technology users, developers, and industry experts to connect, share ideas and best practices, and inspire design creativity.​

Training Webinar: Getting the Most Out of Spectre

In this Cadence Training Webinar, we’ll focus on getting the most out of the Spectre Simulation Platform in terms of the performance/accuracy tradeoff. The goal is to maximize performance while preserving the trusted accuracy for which the Spectre Simulation Platform is renowned. We’ll guide you through each step of the process, from tool selection and initial configuration to troubleshooting convergence and debugging S-parameters.

On-Demand CadenceTECHTALK: Mixed Signal SoC Verification Simplified with Xcelium Simulator

Watch this CadenceTECHTALK™ to learn how Cadence is providing effective verification and debug methodologies using RNM of analog blocks for mixed-signal SoC verification.

On-Demand CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis

Next session in "Adopting a Faster, More Efficient Path to Multi-Chiplet Design" webinar series will help you to get a chip-centric perspective on performing PI and thermal integrity analysis in 3D-ICs from early planning to signoff.

Training Webinar: A Step Change in Custom IC Layout Productivity with Virtuoso Studio

This webinar highlights Cadence’s new productivity features and Virtuoso Studio’s improved performance for core layout. We’ll demonstrate in-design and in-memory signoff DRC and FILL with iPegasus Verification System for Virtuoso Studio as well as the seamless integration of the Innovus Implementation System. We’ll showcase how Virtuoso Studio helps to automate design migration across process nodes.

On-Demand CadenceTECHTALK: Cadence Integrated Platform Solution for 3D-IC Design (Taiwan)

This webinar will discuss technology that proactively looks ahead through integrated early analysis, and addresses all aspects of 3D-IC design comprehensively, including system planning, packaging, implementation, analysis, and system-level signoff. It will discuss requirements and implementation flows for InFO, CoWoS, and SoIC, along with unique Pseudo-3D exploration capabilities that enable PPA push and the feasibility of 2D to 3D design conversion.

On-Demand CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles

Join this next webinar in "Adopting a Faster, More Efficient Path to Multi-Chiplet Design" series to learn about the different approaches to 3D partitioning, implementation, and unique capabilities available with the Cadence® Integrity™ 3D-IC platform for bump planning, interposer routing, and top-down 3D partitioning and implementation.

On-Demand CadenceTECHTALK: Helium Virtual and Hybrid Studio (Taiwan)

In this CadenceTECHTALK, we will show you the configuration and basic features of Cadence® Helium ™ Virtual and Hybrid Studio, a platform that accelerates the creation of virtual and hybrid prototypes of complex systems.

On-Demand CadenceTECHTALK: Efficient Multi-Chiplet Design with Cadence Integrity 3D-IC Unified Platform

Join the first session of a new CadenceTECHTALK series "Adopting a Faster, More Efficient Path to Multi-Chiplet Design" and learn about different packaging styles, innovative multi-technology database, integrated system planner, and an embedded analysis flow manager inside the Integrity 3D-IC platform, which provide a comprehensive, yet modular multi-chiplet design solution to help shorten the design cycle for all aspects of 3D-IC design and signoff.

2022 MATLAB & Simulink Smart Factory Forum -AI for Data Analytics

Join Cadence at 2022 MATLAB & Simulink Smart Factory Forum -AI for Data Analytics. Free registration to attend the virtual co-speech “System Design Challenges and Solutions for Smart Manufacturing” by Cadence Taiwan and Terasoft.

CadenceTECHTALK: 使用 Protium™ X2 加速复杂 SoC芯片原型验证

This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification.

On-Demand CadenceTECHTALK: Best Practices to Achieve the Highest Performance using Xcelium Logic Simulator

Wondering how you can easily achieve up to 3X exemplary performance gains using Xcelium Logic Simulator. This webinar will provide a handy checklist of best practices covering umbrella performance switches, “access” levels, and simulation profiling to achieve the highest performance using Xcelium.

Training Webinar: Automating Bug Tracking with Verisium Debug and Python

The Verisium™ Debug Platform is optimized for scalability, supporting debugging of simulation runs and emulation, where support for loading large source files and handling huge amounts of probe data is a must. In this Training Webinar, you’ll learn how to automate your debug experience using the Verisium Debug platform with its built-in Python API.

On-Demand CadenceTECHTALK: Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows (Taiwan)

對下一代無線通訊、航太和運輸系統的需求正在推動對高性能、成本敏感的矽晶 RFIC 和 III-V 族化合物半導體單晶微波積體電路 (MMICs) 的需求，這些電路通常集成到先進的系統封裝 (SiP)中。 最新版本的 Cadence® AWR Design Environment® 平台讓產品開發團隊能夠透過Cadence Virtuoso® Design Platform 具備的廣泛射頻(RF) 到毫米波(mmWave) 設計、EM 分析和前後端工作流程的互通性，在更短周轉時間內滿足這些無線系統的高效能要求。 本場線上研討會將講述加速設計上手和平台設計共享的關鍵新功能，以提高工程生產力並確保一次性成功。

CadenceTECHTALK: Static Timing Analysis and Some Important Basics

In this webinar, we will discuss STA concepts through the definition of the basics: delays, timing checks, clocks, exceptions, etc. We will also present the way to describe and constrain these in SDC format. We finally see how SDC constraints are connected to the Cadence® Innovus™ CCOpt clock tree engine.

CadenceTECHTALK:如何用 Protium企业级原型设计工具提高生产率，降低成本

Join our webinar as we identify the key requirements and challenges with prototyping, and how using enterprising prototyping systems like Cadence’s Protium system reduce the costs associated with them.

On-Demand CadenceTECHTALK:Reduce Turnaround Times with an RF/microwave Front-to-Back PCB Workflow (Taiwan)

在專門設計環境中開發的射頻/微波 IP 必須轉移到 PCB 繪製軟體中，在軟體中，生產限制、設計規則檢查 (DRC)、電路佈局驗證 (LVS) 以及企業認可的組件，才能與功率及電子設備整合操作。 RF 設計數據（設計圖和佈局）的傳輸通常由佈局團隊手動重新輸入由RF團隊所提供的資訊，浪費了大量的時間和精力。 Cadence® AWR Design Environment® 平台和 Allegro® PCB 設計軟體之間的工作流程互通性使 RF 和佈局團隊能夠更有效地共享數據，減少設計周轉時間並避免因手動輸入導致的潛在錯誤。本場線上研討會將介紹從 RF 到 PCB 的工作流程，並重點介紹設計團隊如何提高生產力和縮短上市時間的方法。

(On-demand) Cadence and Rohde & Schwarz Joint Webinar: 從設計到實現 RF待測物 — EDA模擬中RF功率放大器線性化的優勢 (Taiwan)

R&S與 Cadence 合作開發的新解決方案，可增強廣泛用於執行 EDA 模擬的功能，允許在 EDA 系統模擬和硬體測試中使用真實信號，從而簡化 RF 零件和系統的開發過程。 This webinar is intended for engineers who design RF frontends and RF power amplifiers and striving for the best possible error vector magnitude (EVM) performance.We will introduce a new joint solution for linearization developed together with R&S.

CadenceTECHTALK:智慧系統設計新突破！以 Optimality AI 引擎 優化設計生產力(Taiwan))

本場線上研討會為各位介紹 Cadence® Optimality™ 智慧系統引擎 (Intelligent System Explorer)，不僅能協助加速產品上市並降低設計風險，透過 AI 技術探索關鍵參數，Optimality Explorer 提供的優化設計比傳統手動方法平均快 10 倍，更在某些設計上實現了高達 100 倍的加速！歡迎您加入我們 2023 年第一場線上研討會，透過專業講師的介紹與產品 demo 更深入瞭解 Cadence® Optimality™ 智慧系統引擎。 Cadence® Optimality™ Intelligent System Explorer delivers optimized designs on average 10X faster than traditional manual methods, with up to a 100X speedup realized on some designs.Register for this webinar to learn more about Cadence® Optimality™ Intelligent System Explorer.

CadenceTECHTALK:Certus 突破大型晶片設計收斂與簽核時效挑戰(Taiwan)

本次線上研討會，將由Cadence 應用工程處長Jason介紹Cadence Certus 設計收斂解決方案，首創全自動化作業環境，如何同時加速設計時程及整個設計收斂週期— 從簽核優化到佈線、靜態時序分析 (STA) 和萃取，由數周縮短到一個晚上即可輕鬆完成。 Cadence Certus線上研討會即刻開放報名，歡迎加入! The Cadence Certus Closure Solution is the industry's first fully automated and massively distributed environment for full-chip optimization and signoff. Welcome to join us and learn more about this exciting new product.

On-Demand CadenceTECHTALK: Accelerating Complex SoC Prototyping with Protium X2

This CadenceTECHTALK will offer an overview of the Protium™ Enterprise Prototyping Platform for fast hardware and software verification. We will review the traditional prototyping challenges of complex SoCs using a 5G AI-enabled mobile SoC case study—RTL changes required for clocks management, memories, interfaces, multi-FPGA partitioning, and multi-user support. Learn how the Protium X2 platform features and solutions solve these challenges while accelerating the hardware/software co-design verification schedule.

Cadence TECHTALK: Xcelium Apps：包罗万象的仿真

本次CadenceTECHTALK将全面介绍Xcelium Apps的产品组合，其中包括机器学习，混合信号，多核技术，安全验证，功耗Playback以及X-pessimism Removal。您将了解如何将本地集成的Xcelium Apps无缝混合并搭配，以更快实现验证目标。

On-Demand: CadenceTECHTALK: Analog Fault Injection Simplifies ISO 26262 Compliance

As the automotive market moves toward electrified drivetrains and autonomous driving systems, chip makers increasingly need to design integrated mixed-signal chips that meet the ISO 26262 automotive certification. Join this CadenceTECHTALK™ and discover an easy and fast way to perform the three basic steps: fault identification, fault simulation, and data analysis. Learn about an efficient analog fault injection methodology that supports observation and detection points in the analog and digital domains.

CadenceTECHTALK:使用Xcelium Logic Simulator获得最优性能

Wondering how you can easily achieve up to 3X exemplary performance gains using Xcelium Logic Simulator. This webinar provides a handy checklist of best practices covering umbrella performance switches, “access” levels, and simulation profiling to achieve the highest performance using Xcelium.

Arm Tech Symposia 2022 (China)

Join Cadence at Arm Tech Symposia China 2022 and see how Cadence optimizes PPA and verification processes. Please come to join us and learn about our best solutions for customers.

CadenceCONNECT: Digital Full Flow Technology Day

In this full-day, in-person seminar, we will discuss the entire portfolio of the Cadence® integrated digital full flow, which offers innovations that go across individual tool boundaries by integrating core engines and key technologies that allow you to beat your PPA goals ahead of schedule.

CadenceLIVE Europe 2022

CadenceLIVE Europe 2022 will be held on November 21-22 at the Park Hilton Hotel in Munich. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

DVCon Europe 2022

Join Matt Graham, Product Engineering Group Director, on December 6 at 4pm for his presentation on Verification 2.0 – Multi-Engine, Multi-Run – AI-Driven Verification. This talk covers some of the near-term opportunities for applying AI and ML pragmatically to verification problems and presents potential future directions for AI and ML area. Be sure to visit booth #601 to learn how Cadence is leveraging big data and AI to optimize verification productivity and efficiency with the Verisium™ platform.

CES 2023

Want to see exciting technology that is behind some of the biggest innovations at CES? Book a meeting now to visit the Cadence® invitation-only suites at CES 2023, January 5-8 at the Venetian Expo, Level 2, Titian 2201B.

2022 EDA Workshop (Taiwan)

2022 電子設計自動化研討會將於12/10 &12/11於新竹關西舉辦，除了延續提升 EDA 產學界國際競爭力，也會探索產學界如何因應未來 EDA 與電子產業的變化、營造 EDA 領域人才創業的氛圍，以持續帶動國內 EDA 領域之研究發展。Join Cadence speech at EDA workshop to learn about 「The Future of Intelligent Chip Design」and visit our booth to know about Cadence and EDA industry.

CadenceLIVE Taiwan 2022

CadenceLIVE Taiwan 2022 will be held on September 1st at Sheraton Hsinchu Hotel. Attendees have the opportunity to attend captivating keynotes, interesting user presentations, and interact with industry leaders and Cadence experts. Register today to secure your spot.

CadenceCONNECT: Taiwan Verification Seminar

This seminar will cover, not only our latest product, Verisium AI-Driven Verification Platform, a suite of applications leveraging big data and AI to optimize verification productivity and efficiency, but many verification topics, including Xcelium Simulation, Verisium Debug Analyzer, Jasper RTL Apps, DPA for early power profiling, finally, System VIP on system verification. Come join us!

2022 Cadence中国技术巡回研讨会 - 杭州站

2022 CadenceCONNECT: China Technology Day is coming soon! This year we will hold seminar in many cities including Hangzhou. Cadence will bring you best practices and ideas. Come and join us!

ICECS 2022

The 29th IEEE International Conference on Electronics Circuits and Systems (ICECS) is an international conference dedicated to circuits and systems. Early career researchers and post graduate students can attend the Young Professional track to hear from Ciaran Haughey, Cadence IP team, on “What’s in the Locker? Verification Techniques for Interface Controller IP”

Technology on Tour: Club Verification Munich 2018 Proceedings

Download the proceedings from the Club Verification Munich event.

CadenceCONNECT: Custom IC Day

Cadence is pleased to bring you a series of free CadenceCONNECT seminars focusing on its Custom IC technologies. Join us to see how you can save time with optimized, automated design platforms for complex ICs.

31st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

VLSI-SoC 2023 explores the state-of-the-art in the areas of Very Large-Scale Integration (VLSI) and System-on-Chip (SoC) design. The purpose of VLSI-SoC is to provide a forum to exchange ideas and showcase academic as well as industrial research in architectures, circuits, devices, design automation, verification, test, and security, within digital, analog, and mixed-signal systems. Ziyad Hanna, Corporate VP, Research & Development for the System and Verification group will deliver a keynote talk and Cadence will host a workshop for the attendees.

CadenceLIVE Boston 2022

CadenceLIVE Boston 2022 will be held on September 14 at the Boston Marriott Burlington in Burlington, MA. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

HiFiLeD Symposium 2022

Join us at HiFiLeD Symposium in December 2022. The topics will be range from issues concerning the complexity, reliability, accuracy and uncertainties in generating the High-Fidelity LES/DNS data, to their application towards turbulence and transition modeling. It will include progress on the underlying high-order numerical methods (HOMs), innovative approaches for CPU acceleration for LES and DNS, exploitation of massive parallel architectures, efficient post-processing on massive parallel hardware, innovative machine learning methods, as well as experimental data. Moreover, the Symposium offers the opportunity to communicate and exchange knowledge for academic researchers, graduate students, industrial engineers, as well as industrial R&D managers and consultants working in the fields of turbulent flow modeling, simulations, measurements, and multidisciplinary CFD applications.

CadenceLIVE India 2022

CadenceLIVE India 2022 will be held on September 14-15 at the Radisson Blu Bengaluru Outer Ring Road Hotel in Bangalore. It features peer presentations that offer solutions for today’s design challenges that will impact tomorrow’s products.

CadenceCONNECT: Club Formal India

Cadence is pleased to once again bring you CadenceCONNECT: Club Formal, a platform for formal verification experts to come together and discuss the latest in formal technologies, including challenges, benefits, and best practices. Hear from your peers on how they are using formal verification techniques in their flows and interact with members of the Cadence® R&D team to discuss the technology, roadmap, and use cases. In this in-person seminar, you will hear an industry keynote, a Cadence R&D keynote on the latest in JasperTM technology, and several users who will discuss best practices. Plus, we will have deep technical demos and presentations by Cadence formal experts.

2024 Cadence中国技术巡回研讨会 — 设计IP研讨会专场

2024 CadenceCONNECT: China Technology Day is coming soon! This year we will hold seminar in many cities. Cadence will bring you best practices and ideas. Come and join us!

DATE 2023

The Design, Automation and Test in Europe (DATE) conference is the main European event bringing together designers and design automation users, researchers, and vendors, as well as specialists in the hardware and software design, test, and manufacturing of electronic circuits and systems. DATE puts a strong emphasis on both technology and systems, covering ICs/SoCs, reconfigurable hardware and embedded systems as well as embedded software.

CadenceTECHTALK: Large Eddy CFD Simulation for Automotive Aerodynamics

Webinar (India): Leveraging In-Design DFM to Reduce Post-Layout Signoff Iterations

Join this free live webinar and learn how Cadence’s Allegro PCB DesignTrue DFM Technology offers industry’s first in-design DFM solution addressing manufacturing checks in real time as you design.

CadenceTECHTALK: Applying AI/ML Technology for Rapid Design Optimization

Accelerate Time to Market by Enhancing Cross-Team Collaboration in Real-Time

In this joint webinar with OpsHub, we will discuss how teams can proactively manage requirements compliance with real-time data by establishing full traceability and collaboration between verification requirements, verification test cases and outcomes. Join our subject matter experts in this webinar to understand how connecting vManager data bidirectionally with other tools in real-time.

On-Demand CadenceTECHTALK (Japan): AWRオンライン・セミナー 2020 -August （オンデマンド）

AWR製品の技術的なご紹介、ケイデンスの各種製品と連携したソリューションについてご紹介します。今回は、今年5月にリリースしたAWR製品 バージョン15について、AWR製品をご愛用頂いてきたお客様には製品の更新情報、あまりご存知でないお客様には製品の目指す方向をお伝えできるよう更新内容を工夫してお伝えします。

Webinar: Genus iSpatial - Better Predictability and PPA (Hebrew)

Please join this free one-hour live webinar in Hebrew and hear about how Cadence can help you to meet or exceed your power, performance, and area (PPA) targets on complex SoC designs while maintaining quality and design schedule. Limited to Cadence customers with access to the digital implementation flow.